Espressif ESP32 Technical Reference Manual page 149

7 SPI Controller (SPI)
31
0 0 0 0 0 0 0
SPI_SLV_WRBUF_DUMMY_CYCLELEN It indicates the number of SPI clock cycles minus one for the
dummy phase for write-data operations. It is only valid when SPI_SLV_WRBUF_DUMMY_EN is set
to 1 in slave half-duplex mode. (R/W)
SPI_SLV_RDBUF_DUMMY_CYCLELEN It indicates the number of SPI clock cycles minus one for the
dummy phase for read-data operations. It is only valid when SPI_SLV_RDBUF_DUMMY_EN is set
to 1 in slave half-duplex mode. (R/W)
SPI_SLV_WRSTA_DUMMY_CYCLELEN It indicates the number of SPI clock cycles minus one
for the dummy phase for write-status register operations.
SPI_SLV_WRSTA_DUMMY_EN is set to 1 in slave half-duplex mode. (R/W)
SPI_SLV_RDSTA_DUMMY_CYCLELEN It indicates the number of SPI clock cycles minus one
for the dummy phase for read-status register operations.
SPI_SLV_RDSTA_DUMMY_EN is set to 1 in slave half-duplex mode. (R/W)
31
0 0 0 0 0 0 0
SPI_SLV_WRSTA_CMD_VALUE Reserved.
SPI_SLV_RDSTA_CMD_VALUE Reserved.
SPI_SLV_WRBUF_CMD_VALUE Reserved.
SPI_SLV_RDBUF_CMD_VALUE Reserved.
Espressif Systems
Register 7.17. SPI_SLAVE2_REG (0x40)
24 23
0 0x000
Register 7.18. SPI_SLAVE3_REG (0x44)
24 23
0 0 0 0 0 0 0 0
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16 15
0x000
16 15
0 0 0 0 0 0 0 0
149
8 7
0x000
It is only valid when
It is only valid when
8 7
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
Reset
0
0
Reset