Espressif ESP32 Technical Reference Manual page 506

17 Pulse Count Controller (PCNT)
31 30 29 28 27 26 25
0 0 0 0
PCNT_CH1_LCTRL_MODE_Un
settings will be modified when the control signal is low. (R/W) 0: No modification; 1: Invert
behaviour (increase → decrease, decrease → increase); 2, 3: Inhibit counter modification
PCNT_CH1_HCTRL_MODE_Un
settings will be modified when the control signal is high. (R/W) 0: No modification; 1: Invert
behaviour (increase → decrease, decrease → increase); 2, 3: Inhibit counter modification
PCNT_CH1_POS_MODE_Un
detects a positive edge. (R/W) 1: Increment the counter; 2: Decrement the counter; 0, 3: No
effect on counter
PCNT_CH1_NEG_MODE_Un
tects a negative edge. (R/W) 1: Increment the counter; 2: Decrement the counter; 0, 3: No
effect on counter
PCNT_CH0_LCTRL_MODE_Un
CH0_POS_MODE/CH0_NEG_MODE settings will be modified when the control signal is
low. (R/W) 0: No modification; 1: Invert behaviour (increase → decrease, decrease →
increase); 2, 3: Inhibit counter modification
PCNT_CH0_HCTRL_MODE_Un
CH0_POS_MODE/CH0_NEG_MODE settings will be modified when the control signal is
high. (R/W) 0: No modification; 1: Invert behaviour (increase → decrease, decrease →
increase); 2, 3: Inhibit counter modification
PCNT_CH0_POS_MODE_Un
detects a positive edge. (R/W) 1: Increase the counter; 2: Decrease the counter; 0, 3: No
effect on counter
PCNT_CH0_NEG_MODE_Un
detects a negative edge. (R/W) 1: Increase the counter; 2: Decrease the counter; 0, 3: No
effect on counter
PCNT_THR_THRES1_EN_Un
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Espressif Systems
Register 17.1. PCNT_Un_CONF0_REG (n: 0-7) (0x0+0x0C*n)
24 23 22 21 20 19 18 17
0 0 0
This register configures how the CH1_POS_MODE/CH1_NEG_MODE
This register configures how the CH1_POS_MODE/CH1_NEG_MODE
This register sets the behaviour when the signal input of channel 1
This register sets the behaviour when the signal input of channel 1 de-
This
This
This register sets the behaviour when the signal input of channel 0
This register sets the behaviour when the signal input of channel 0
This is the enable bit for unit n's thres1 comparator. (R/W)
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16 15 14 13 12 11 10 9
0 0 0 1 1 1 1
register configures
register configures
506
0
0x010 Reset
how the
how the
ESP32 TRM (Version 5.2)