Espressif ESP32 Technical Reference Manual page 165

8 SDIO Slave Controller
the SLC0_RXLINK_ADDR bit of SLC0RX_LINK, then set the SLC0_RXLINK_START bit of SLC0RX_LINK. The
DMA will automatically complete the data transfer. Upon completion of the operation, DMA will interrupt the
CPU so that the buffer space can be freed or reused.
8.3.5.2 Receiving Packets from SDIO Host
Transmission of packets from Host to Slave is initiated by the Host. The Slave receives data via DMA and stores
it in RAM. After transmission is completed, the CPU will be interrupted to process the data. The whole
procedure is demonstrated in Figure 8-7.
Figure 8-7. Packet Receiving Procedure (Initiated by Host)
The Host obtains the number of available receiving buffers from the Slave by accessing register
SLC0HOST_TOKEN_RDATA. The Slave CPU should update this value after the receiving DMA linked list is
prepared.
HOSTREG_SLC0_TOKEN1 in SLC0HOST_TOKEN_RDATA stores the accumulated number of available
buffers.
The Host can figure out the available buffer space, using HOSTREG_SLC0_TOKEN1 minus the number of
buffers already used.
If the buffers are not enough, the Host needs to constantly poll the register until there are enough buffers
available.
To ensure sufficient receiving buffers, the Slave CPU must constantly load buffers on the receiving linked list.
The process is shown in Figure 8-8.
Espressif Systems 165 ESP32 TRM (Version 5.2)
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