Espressif ESP32 Technical Reference Manual page 240

10 Ethernet Media Access Controller (MAC)
Bits Name
[31] OWN: Own Bit
[30] IC: Interrupt on Completion
[29] LS: Last Segment
[28] FS: First Segment
[27] DC: Disable CRC
[26] DP: Disable Pad
[25] Reserved
CRCR: CRC Replacement
[24]
Control
Espressif Systems
Table 10-5. Transmit Descriptor 0 (TDES0)
Description
When set, this bit indicates that the descriptor is owned by the
DMA. When this bit is reset, it indicates that the descriptor is
owned by the Host. The DMA clears this bit, either when it com-
pletes the frame transmission or when the buffers allocated to the
descriptor are empty. The ownership bit of the First Descriptor of
the frame should be set after all subsequent descriptors belong-
ing to the same frame have been set. This avoids a possible race
condition between fetching a descriptor and the driver setting an
ownership bit.
When set, this bit sets the Transmit Interrupt (Register 5[0]) after
the present frame has been transmitted. This bit is valid only when
the last segment bit (TDES0[29]) is set.
When set, this bit indicates that the buffer contains the last seg-
ment of the frame. When this bit is set, the TBS1 or TBS2 field in
TDES1 should have a non-zero value.
When set, this bit indicates that the buffer contains the first seg-
ment of a frame.
When this bit is set, the MAC does not append a cyclic redun-
dancy check (CRC) to the end of the transmitted frame. This is
valid only when the first segment (TDES0[28]) is set.
When set, the MAC does not automatically add padding to a frame
shorter than 64 bytes. When this bit is reset, the DMA automati-
cally adds padding and CRC to a frame shorter than 64 bytes, and
the CRC field is added despite the state of the DC (TDES0[27])
bit. This is valid only when the first segment (TDES0[28]) is set.
Reserved
When set, the MAC replaces the last four bytes of the transmitted
packet with recalculated CRC bytes. The host should ensure that
the CRC bytes are present in the frame being transmitted from the
Transmit Buffer. This bit is valid when the First Segment control
bit (TDES0[28]) is set. In addition, CRC replacement is done only
when Bit TDES0[27] is set to 1.
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