Espressif ESP32 Technical Reference Manual page 304

11 I2C Controller (I2C)
31 30
0 0 0 0 0 0 0
I2C_SLAVE_ADDR_10BIT_EN This field is used to enable the slave 10-bit addressing mode in master
mode. (R/W)
I2C_SLAVE_ADDR When configured as an I2C Slave, this field is used to configure the slave ad-
dress. (R/W)
31
0 0 0 0 0 0 0
I2C_TXFIFO_END_ADDR This is the offset address of the last sent data, as described
in nonfifo_tx_thres register.
I2C_TRANS_COMPLETE_INT interrupt is generated. (RO)
I2C_TXFIFO_START_ADDR This is the offset address of the first sent data, as described in non-
fifo_tx_thres register. (RO)
I2C_RXFIFO_END_ADDR This is the offset address of the last received data, as de-
scribed in nonfifo_rx_thres_register. This value refreshes when I2C_RX_REC_FULL_INT or
I2C_TRANS_COMPLETE_INT interrupt is generated. (RO)
I2C_RXFIFO_START_ADDR This is the offset address of the last received data, as described in non-
fifo_rx_thres_register. (RO)
Espressif Systems
Register 11.5. I2C_SLAVE_ADDR_REG (0x0010)
0 0 0 0 0 0 0 0
Register 11.6. I2C_RXFIFO_ST_REG (0x0014)
20 19
0 0 0 0 0 0 0 0
The value refreshes when I2C_TX_SEND_EMPTY_INT or
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15 14
0 0 0 0 0 0 0 0
15 14 10 9
0 0 0 0 0 0 0 0
304
0 0 0 0 0 0 0 0
5 4
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0 Reset
0
0 Reset