Espressif ESP32 Technical Reference Manual page 295

11 I2C Controller (I2C)
Slave controller has hardware support for such a scheme.
Specifically, on the Slave, I2C_FIFO_ADDR_CFG_EN can be set so that the I2C Master can write to a specified
register address inside the I2C Slave memory block. Figure 11-7 shows the Master writing N-bytes of data byte0
~ byte(N-1) from the RAM unit to register address M (determined by addrM in RAM unit) with the Slave. In this
mode, Slave can receive up to 32 bytes of valid data. When Master needs to transmit extra amount of data,
segmented transmission can be enabled.
Figure 11-7. I2C Master Writes to addrM in RAM of Slave with 7-bit Address
If the data size exceeds the capacity of a 14-byte read/write cmd, the END command can be called to en-
able segmented transmission. Figure 11-8 shows the Master writing data to the Slave, in three segments. The
first segment shows the configuration of the Master's commands and the preparation of data in the RAM unit.
When the I2C_TRANS_START bit is enabled, the Master starts transmission. After executing the END command,
the Master will turn off the SCL clock and pull the SCL low to reserve the bus and prevent any other device
from transacting on the bus. The controller will generate an I2C_END_DETECT_INT interrupt to notify the soft-
ware.
Espressif Systems 295 ESP32 TRM (Version 5.2)
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