Espressif ESP32 Technical Reference Manual page 3

Contents
Contents
1 System and Memory
1.1 Introduction
1.2 Features
1.3 Functional Description
1.3.1 Address Mapping
1.3.2 Embedded Memory
1.3.2.1
1.3.2.2
1.3.2.3
1.3.2.4
1.3.2.5
1.3.2.6
1.3.2.7
1.3.2.8
1.3.3 External Memory
1.3.4 Cache
1.3.5 Peripherals
1.3.5.1
1.3.5.2
1.3.5.3
2 Interrupt Matrix (INTERRUPT)
2.1 Overview
2.2 Features
2.3 Functional Description
2.3.1 Peripheral Interrupt Source
2.3.2 CPU Interrupt
2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU
2.3.4 CPU NMI Interrupt Mask
2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source
2.4 Registers
3 Reset and Clock
3.1 System Reset
3.1.1 Introduction
3.1.2 Reset Source
3.2 System Clock
3.2.1 Introduction
3.2.2 Clock Source
3.2.3 CPU Clock
3.2.4 Peripheral Clock
3.2.4.1
Espressif Systems
Internal ROM 0
Internal ROM 1
Internal SRAM 0
Internal SRAM 1
Internal SRAM 2
DMA
RTC FAST Memory
RTC SLOW Memory
Asymmetric PID Controller Peripheral
Non-Contiguous Peripheral Memory Ranges
Memory Speed
APB_CLK
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ESP32 TRM (Version 5.2)