Espressif ESP32 Technical Reference Manual page 210

9 SD/MMC Host Controller
31
CLKSRC_REG Clock divider source for two SD cards is supported. Each card has two bits assigned
to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps
and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value.
00 : Clock divider 0;
01 : Clock divider 1;
10 : Clock divider 2;
11 : Clock divider 3.
In MMC-Ver3.3-only controller, only one clock divider is supported. The cclk_out is always from
clock divider 0, and this register is not implemented. (R/W)
31
CCLK_ENABEL Clock-enable control for two SD card clocks and one MMC card clock is supported.
0: Clock disabled;
1: Clock enabled.
In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_enable[0] is used. (R/W)
Espressif Systems
Register 9.3. CLKSRC_REG (0x000C)
0x000000
Register 9.4. CLKENA_REG (0x0010)
0x00000
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4 3 0
0x0
Reset
2 1 0
0x00000 Reset
ESP32 TRM (Version 5.2)