Espressif ESP32 Technical Reference Manual page 274

10 Ethernet Media Access Controller (MAC)
31
0 0 0 0 0 0 0
WKUPPKTFILTER The MSB (31st bit) must be zero. Bit j[30:0] is the byte mask. If Bit 1/2/3/4 (byte
number) of the byte mask is set, the CRC block processes the filter 0/1/2/3 Offset + j of the
incoming packet (RWKPTR is 0/1/2/3). (R/W)
• RWKPTR is 0:Filter 0 Byte Mask;
• RWKPTR is 1: Filter 1 Byte Mask;
• RWKPTR is 2: Filter 2 Byte Mask;
• RWKPTR is 3: Filter 3 Byte Mask;
• RWKPTR is 4: Bit 3/11/19/27 specifies the address type, defining the destination address
type of the pattern. When the bit is set, the pattern applies to only multicast packets; when
the bit is reset, the pattern applies only to unicast packet for filter 0/1/2/3. Bit 0/8/16/24 is
the enable bit for filter 0/1/2/3;
• RWKPTR is 5: This filter 0/1/2/3 offset register defines the offset (within the packet) from
which the filter 0/1/2/3 examines the packets;
• RWKPTR is 6: This filter 0 (bit[15:0])/1 (bit[31:16]) CRC16 register contains the CRC16 value
calculated from the pattern and also the byte mask programmed to the wake-up filter register
block; The polynomial:
16
G(x) = x
• RWKPTR is 7: This filter 2 bit[15:0])/3(bit[31:16]) CRC16 register contains the CRC16 value
calculated from the pattern and also the byte mask programmed to the wake-up filter register
block. The polynomial:
16
G(x) = x
Espressif Systems
Register 10.21. PMT_RWUFFR_REG (0x1028)
0 0 0 0 0 0 0 0
15 2
+ x + x + 1.
15 2
+ x + x + 1.
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0 0 0 0 0 0 0 0
274
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0
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