Espressif ESP32 Technical Reference Manual page 273

10 Ethernet Media Access Controller (MAC)
Continued from the previous page...
MTLRFRCS This field gives the state of the Rx FIFO read Controller: (RO)
2'b00: IDLE state.
2'b01: Reading frame data.
2'b10: Reserved.
2'b11: Flushing the frame data and status.
MTLRFWCAS When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is
transferring a received frame to the FIFO. (RO)
MACRFFCS When high, this field indicates the active state of the FIFO Read and Write controllers
of the MAC Receive Frame Controller Module. MACRFFCS[1] represents the status of FIFO Read
controller. MACRFFCS[0] represents the status of small FIFO Write controller. (RO)
MACRPES When high, this bit indicates that the MAC MII receive protocol engine is actively receiv-
ing data and not in IDLE state. (RO)
Espressif Systems
Register 10.20. EMACDEBUG_REG (0x1024)
273
Submit Documentation Feedback
ESP32 TRM (Version 5.2)