Espressif ESP32 Technical Reference Manual page 611

27 Memory Management and Protection Units (MMU, MPU)
27 Memory Management and Protection Units (MMU, MPU)
27.1 Introduction
Every peripheral and memory section in the ESP32 is accessed through either an MMU (Memory Management
Unit) or an MPU (Memory Protection Unit). An MPU can allow or disallow the access of an application to a mem-
ory range or peripheral, depending on what kind of permission the OS has given to that particular application.
An MMU can perform the same operation, as well as a virtual-to-physical memory address translation. This can
be used to map an internal or external memory range to a certain virtual memory area. These mappings can
be application-specific. Therefore, each application can be adjusted and have the memory configuration that
is necessary for it to run properly. To differentiate between the OS and applications, there are eight Process
Identifiers (or PIDs) that each application, or OS, can run. Furthermore, each application, or OS, is equipped
with their own sets of mappings and rights.
27.2 Features
• Eight processes in each of the PRO_CPU and APP_CPU
• MPU/MMU management of on-chip memories, off-chip memories, and peripherals, based on process ID
• On-chip memory management by MPU/MMU
• Off-chip memory management by MMU
• Peripheral management by MPU
27.3 Functional Description
27.3.1 PID Controller
In the ESP32, a PID controller acts as an indicator that signals the MMU/MPU the owner PID of the code that
is currently running. The intention is that the OS updates the PID in the PID controller every time it switches
context to another application. The PID controller can detect interrupts and automatically switch PIDs to that of
the OS, if so configured.
There are two peripheral PID controllers in the system, one for each of the two CPUs in the ESP32. Having a
PID controller per CPU allows running different processes on different CPUs, if so desired.
27.3.2 MPU/MMU
The MPU and MMU manage on-chip memories, off-chip memories, and peripherals. To do this they are based
on the process of accessing the peripheral or memory region. More specifically, when a code tries to access a
MMU/MPU-protected memory region or peripheral, the MMU or MPU will receive the PID from the PID generator
that is associated with the CPU on which the process is running.
For on-chip memory and peripherals, the decisions the MMU and MPU make are only based on this PID, whereas
the specific CPU the code is running on is not taken into account. Subsequently, the MMU/MPU configuration
for the internal memory and peripherals allows entries only for the eight different PIDs. In contrast, the MMU
moderating access to the external memory takes not only the PID into account, but also the CPU the request is
coming from. This means that MMUs have configuration options for every PID when running on the APP_CPU, as
well as every PID when running on the PRO_CPU. While, in practice, accesses from both CPUs will be configured
to have the same result for a specific process, doing so is not a hardware requirement.
Espressif Systems 611
Submit Documentation Feedback
ESP32 TRM (Version 5.2)