Espressif ESP32 Technical Reference Manual page 584

22 AES Accelerator (AES)
Bit 0 and bit 1 in AES_ENDIAN_REG define the key endianness. For detailed information, please see Table 22-3,
Table 22-4 and Table 22-5. w[0] ~ w[3] in Table 22-3, w[0] ~ w[5] in Table
are "the first Nk words of the expanded key" as specified in "5.2: Key Expansion" of FIPS PUB 197. "Column Bit"
specifies the bytes in the word from w[0] to w[7]. The bytes of AES_KEY_n_REG comprise "the first Nk words
of the expanded key".
Text Endianness
Bit 2 and bit 3 in AES_ENDIAN_REG define the endianness of input text, while Bit 4 and Bit 5 define the endian-
ness of output text. The input text refers to the plaintext in AES-128/192/256 encryption and the ciphertext in
decryption. The output text refers to the ciphertext in AES-128/192/256 encryption and the plaintext in decryp-
tion. For details, please see Table 22-2. "State" in Table
197: "The AES algorithm operations are performed on a two-dimensional array of bytes called the State". The
ciphertext or plaintexts stored in each byte of AES_TEXT_m_REG comprise the State.
AES_ENDIAN_REG[3]/[5] AES_ENDIAN_REG[2]/[4]
0 0
0 1
1 0
1 1
Espressif Systems
22-2
Table 22-2. AES Text Endianness
State
0
0 AES_TEXT_3_REG[31:24]
1 AES_TEXT_3_REG[23:16]
r
2 AES_TEXT_3_REG[15:8]
3 AES_TEXT_3_REG[7:0]
State
0
0 AES_TEXT_3_REG[7:0]
1 AES_TEXT_3_REG[15:8]
r
2 AES_TEXT_3_REG[23:16]
3 AES_TEXT_3_REG[31:24]
State
0
0 AES_TEXT_0_REG[31:24]
1 AES_TEXT_0_REG[23:16]
r
2 AES_TEXT_0_REG[15:8]
3 AES_TEXT_0_REG[7:0]
State
0
0 AES_TEXT_0_REG[7:0]
1 AES_TEXT_0_REG[15:8]
r
2 AES_TEXT_0_REG[23:16]
3 AES_TEXT_0_REG[31:24]
584
Submit Documentation Feedback
22-4 and w[0] ~ w[7] in Table
is defined as that in "3.4: The State" of FIPS PUB
Plaintext/Ciphertext
c
1 2
AES_TEXT_2_REG[31:24] AES_TEXT_1_REG[31:24]
AES_TEXT_2_REG[23:16] AES_TEXT_1_REG[23:16]
AES_TEXT_2_REG[15:8] AES_TEXT_1_REG[15:8]
AES_TEXT_2_REG[7:0] AES_TEXT_1_REG[7:0]
c
1 2
AES_TEXT_2_REG[7:0] AES_TEXT_1_REG[7:0]
AES_TEXT_2_REG[15:8] AES_TEXT_1_REG[15:8]
AES_TEXT_2_REG[23:16] AES_TEXT_1_REG[23:16]
AES_TEXT_2_REG[31:24] AES_TEXT_1_REG[31:24]
c
1 2
AES_TEXT_1_REG[31:24] AES_TEXT_2_REG[31:24]
AES_TEXT_1_REG[23:16] AES_TEXT_2_REG[23:16]
AES_TEXT_1_REG[15:8] AES_TEXT_2_REG[15:8]
AES_TEXT_1_REG[7:0] AES_TEXT_2_REG[7:0]
c
1 2
AES_TEXT_1_REG[7:0] AES_TEXT_2_REG[7:0]
AES_TEXT_1_REG[15:8] AES_TEXT_2_REG[15:8]
AES_TEXT_1_REG[23:16] AES_TEXT_2_REG[23:16]
AES_TEXT_1_REG[31:24] AES_TEXT_2_REG[31:24]
ESP32 TRM (Version 5.2)
22-5
3
AES_TEXT_0_REG[31:24]
AES_TEXT_0_REG[23:16]
AES_TEXT_0_REG[15:8]
AES_TEXT_0_REG[7:0]
3
AES_TEXT_0_REG[7:0]
AES_TEXT_0_REG[15:8]
AES_TEXT_0_REG[23:16]
AES_TEXT_0_REG[31:24]
3
AES_TEXT_3_REG[31:24]
AES_TEXT_3_REG[23:16]
AES_TEXT_3_REG[15:8]
AES_TEXT_3_REG[7:0]
3
AES_TEXT_3_REG[7:0]
AES_TEXT_3_REG[15:8]
AES_TEXT_3_REG[23:16]
AES_TEXT_3_REG[31:24]