Espressif ESP32 Technical Reference Manual page 309

11 I2C Controller (I2C)
31
0 0 0 0 0
I2C_TX_SEND_EMPTY_INT_ST The masked interrupt status bit for the
interrupt. (RO)
I2C_RX_REC_FULL_INT_ST The masked interrupt status bit for the
rupt. (RO)
I2C_ACK_ERR_INT_ST The masked interrupt status bit for the
I2C_TRANS_START_INT_ST The masked interrupt status bit for the
(RO)
I2C_TIME_OUT_INT_ST The masked interrupt status bit for the
I2C_TRANS_COMPLETE_INT_ST The
I2C_TRANS_COMPLETE_INT
I2C_MASTER_TRAN_COMP_INT_ST The
I2C_MASTER_TRAN_COMP_INT
I2C_ARBITRATION_LOST_INT_ST The
I2C_ARBITRATION_LOST_INT
I2C_END_DETECT_INT_ST The masked interrupt status bit for the
(RO)
31
0 0 0 0 0 0 0
I2C_SDA_HOLD_TIME This register is used to configure the time to hold the data after the negative
edge of SCL, in APB clock cycles. (R/W)
Espressif Systems
Register 11.11. I2C_INT_STATUS_REG (0x002c)
0 0 0 0 0 0 0 0
masked
interrupt. (RO)
interrupt. (RO)
masked
interrupt. (RO)
Register 11.12. I2C_SDA_HOLD_REG (0x0030)
0 0 0 0 0 0 0 0
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13 12 11
0 0 0 0 0 0 0 0
I2C_RX_REC_FULL_INT
I2C_ACK_ERR_INT
I2C_TRANS_START_INT
I2C_TIME_OUT_INT
interrupt
masked interrupt
interrupt
I2C_END_DETECT_INT
10 9
0 0 0 0 0 0 0 0
309
10 9 8 7 6 5 3
0 0 0 0 0 0 0
Reset
I2C_TX_SEND_EMPTY_INT
interrupt. (RO)
interrupt.
interrupt. (RO)
status bit for
status bit for
status bit for
interrupt.
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
inter-
the
the
the
0
0 Reset