Espressif ESP32 Technical Reference Manual page 102

5 DPort Registers
Name
DPORT_DMMU_TABLE11_REG
DPORT_DMMU_TABLE12_REG
DPORT_DMMU_TABLE13_REG
DPORT_DMMU_TABLE14_REG
DPORT_DMMU_TABLE15_REG
APP_CPU controller registers
DPORT_APPCPU_CTRL_REG_A_REG
DPORT_APPCPU_CTRL_REG_B_REG
DPORT_APPCPU_CTRL_REG_C_REG
DPORT_APPCPU_CTRL_REG_D_REG
Peripheral clock gating and reset registers
DPORT_PERI_CLK_EN_REG
DPORT_PERI_RST_EN_REG
DPORT_PERIP_CLK_EN_REG
DPORT_PERIP_RST_EN_REG
DPORT_WIFI_CLK_EN_REG
DPORT_WIFI_RST_EN_REG
Espressif Systems
Description
MMU register 1 for internal
SRAM 2
MMU register 1 for internal
SRAM 2
MMU register 1 for internal
SRAM 2
MMU register 1 for internal
SRAM 2
MMU register 1 for internal
SRAM 2
reset for APP_CPU
clock gate for APP_CPU
stall for APP_CPU
boot address for APP_CPU
clock gate for peripherals
reset for peripherals
clock gate for peripherals
reset for peripherals
clock gate for Wi-Fi
reset for Wi-Fi
102
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Address Access
0x3FF00570 R/W
0x3FF00574 R/W
0x3FF00578 R/W
0x3FF0057C R/W
0x3FF00580 R/W
0x3FF0002C R/W
0x3FF00030 R/W
0x3FF00034 R/W
0x3FF00038 R/W
0x3FF0001C R/W
0x3FF00020 R/W
0x3FF000C0 R/W
0x3FF000C4 R/W
0x3FF000CC R/W
0x3FF000D0 R/W
ESP32 TRM (Version 5.2)