Espressif ESP32 Technical Reference Manual page 39

2 Interrupt Matrix (INTERRUPT)
ister of the PRO_CPU (or APP_CPU). The peripheral interrupt configuration register corresponds to the
peripheral interrupt source Source_X. In Table
ripheral Interrupt Configuration Register" correspond to the peripheral interrupt sources listed in "Peripheral
Interrupt Source - Name".
• Interrupt_P stands for CPU peripheral interrupt, numbered as Num_P. Num_P can take the ranges 0 ~ 5,
8 ~ 10, 12 ~ 14, 17 ~ 28, 30 ~ 31.
• Interrupt_I stands for the CPU internal interrupt numbered as Num_I. Num_I can take values 6, 7, 11, 15, 16,
29.
Using this terminology, the possible operations of the Interrupt Matrix controller can be described as fol-
lows:
• Allocate peripheral interrupt source Source_X to CPU (PRO_CPU or APP_CPU)
Set PRO_X_MAP_REG (or APP_X_MAP_REG) to Num_P. Num_P can be any CPU peripheral interrupt num-
ber. CPU interrupts can be shared between multiple peripherals (see below).
• Disable peripheral interrupt source Source_X for CPU (PRO_CPU or APP_CPU)
Set PRO_X_MAP_REG (or APP_X _MAP_REG) for peripheral interrupt source to any Num_I. The specific
choice of internal interrupt number does not change behaviour, as none of the interrupt numbered as
Num_I is connected to either CPU.
• Allocate multiple peripheral sources
Set multiple PRO_Xn_MAP_REG (APP_Xn_MAP_REG) to the same Num_P. Any of these peripheral inter-
rupts will trigger CPU Interrupt_P.
2.3.4 CPU NMI Interrupt Mask
The Interrupt Matrix temporarily masks all peripheral interrupt sources allocated to PRO_CPU's ( or APP_CPU's )
NMI interrupt, if it receives the signal PRO_CPU NMI Interrupt Mask ( or APP_CPU NMI Interrupt Mask ) from the
peripheral PID Controller, respectively.
2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source
The current interrupt status of a peripheral interrupt source can be read via the bit value in
(APP_INTR_STATUS_REG_n), as shown in the mapping in Table 2-1.
2.4 Registers
The interrupt matrix registers are part of the DPORT registers and are described in Section
Registers.
Espressif Systems
2-1 the registers listed under "PRO_CPU (APP_CPU) - Pe-
Source_Xn ORed to PRO_CPU (APP_CPU) peripheral interrupt
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PRO_INTR_STATUS_REG_n
5.4 in Chapter 5 DPort
ESP32 TRM (Version 5.2)