Espressif ESP32 Technical Reference Manual page 616

27 Memory Management and Protection Units (MMU, MPU)
MMU Mapping
For each of the SRAM0 and SRAM2 MMUs, access rights and virtual to physical page mapping are done by
a set of 16 registers. In contrast to most of the other MMUs, each register controls a physical page, not a
virtual one. These registers control which of the PIDs have access to the physical memory, as well as which
virtual page maps to this physical page. The bits in the register are described in Table 27-7. Keep in mind that
these registers only govern accesses from processes with PID 2 to 7; PID 0 and 1 always have full read and
write access to all pages and no virtual-to-physical mapping is done. In other words, if a process with a PID
of 0 or 1 accesses virtual page x, the access will always go to physical page x, regardless of these register
settings. These registers, as well as the page size selection registers DPORT_IMMU_PAGE_MODE_REG and
DPORT_DMMU_PAGE_MODE_REG, are only writable from a process with PID 0 or 1.
Table 27-7. DPORT_DMMU_TABLEn_REG & DPORT_IMMU_TABLEn_REG
[6:4] Access rights for PID 2 ~ 7
0 None of PIDs 2 ~ 7 have access.
1 All of PIDs 2 ~ 7 have access.
2 Only PID 2 has access.
3 Only PID 3 has access.
4 Only PID 4 has access.
5 Only PID 5 has access.
6 Only PID 6 has access.
7 Only PID 7 has access.
Differences Between SRAM0 and SRAM2 MMU
The memory governed by the SRAM0 MMU is accessed through the processors I-bus, while the processor
accesses the memory governed by the SRAM2 MMU through the D-bus. Thus, the normal envisioned use
is for the code to be stored in the SRAM0 MMU pages and data in the MMU pages of SRAM2. In general,
applications running under a PID of 2 to 7 are not expected to modify their own code, because for these PIDs
access to the MMU pages of SRAM0 is read-only. These applications must, however, be able to modify their
data section, so that they are allowed to read as well as write MMU pages located in SRAM2. As stated before,
processes running under PID 0 or 1 always have full read-and-write access to both memory ranges.
DMA MPU
Applications may want to configure the DMA to send data straight from or to the peripherals they can control.
With access to DMA, a malicious process may also be able to copy data from or to a region it cannot normally
access. In order to be secure against that scenario, there is a DMA MPU which can be used to disallow DMA
Espressif Systems
[3:0] Address authority
0x00 Virtual page 0 accesses this physical page.
0x01 Virtual page 1 accesses this physical page.
0x02 Virtual page 2 accesses this physical page.
0x03 Virtual page 3 accesses this physical page.
0x04 Virtual page 4 accesses this physical page.
0x05 Virtual page 5 accesses this physical page.
0x06 Virtual page 6 accesses this physical page.
0x07 Virtual page 7 accesses this physical page.
0x08 Virtual page 8 accesses this physical page.
0x09 Virtual page 9 accesses this physical page.
0x10 Virtual page 10 accesses this physical page.
0x11 Virtual page 11 accesses this physical page.
0x12 Virtual page 12 accesses this physical page.
0x13 Virtual page 13 accesses this physical page.
0x14 Virtual page 14 accesses this physical page.
0x15 Virtual page 15 accesses this physical page.
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