Espressif ESP32 Technical Reference Manual page 382

13 UART Controller (UART)
31
0 0 0 0 0 0 0
UHCI_SEND_A_REG_Q_INT_ENA The interrupt enable bit for the
rupt. (R/W)
UHCI_SEND_S_REG_Q_INT_ENA The interrupt enable bit for the
rupt. (R/W)
UHCI_OUT_TOTAL_EOF_INT_ENA The interrupt enable bit for the
rupt. (R/W)
UHCI_OUTLINK_EOF_ERR_INT_ENA The interrupt enable bit for the
interrupt. (R/W)
UHCI_IN_DSCR_EMPTY_INT_ENA The interrupt enable bit for the
terrupt. (R/W)
UHCI_OUT_DSCR_ERR_INT_ENA The interrupt enable bit for the
rupt. (R/W)
UHCI_IN_DSCR_ERR_INT_ENA The interrupt enable bit for the
(R/W)
UHCI_OUT_EOF_INT_ENA The interrupt enable bit for the
UHCI_OUT_DONE_INT_ENA The interrupt enable bit for the
UHCI_IN_ERR_EOF_INT_ENA The interrupt enable bit for the
(R/W)
UHCI_IN_SUC_EOF_INT_ENA The interrupt enable bit for the
(R/W)
UHCI_IN_DONE_INT_ENA The interrupt enable bit for the
UHCI_TX_HUNG_INT_ENA The interrupt enable bit for the
UHCI_RX_HUNG_INT_ENA The interrupt enable bit for the
UHCI_TX_START_INT_ENA The interrupt enable bit for the
UHCI_RX_START_INT_ENA The interrupt enable bit for the
Espressif Systems
Register 13.32. UHCI_INT_ENA_REG (0xC)
17
0 0 0 0 0 0 0 0
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16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
UHCI_SEND_A_REG_Q_INT
UHCI_SEND_S_REG_Q_INT
UHCI_OUT_TOTAL_EOF_INT
UHCI_OUTLINK_EOF_ERR_INT
UHCI_IN_DSCR_EMPTY_INT
UHCI_OUT_DSCR_ERR_INT
UHCI_IN_DSCR_ERR_INT
UHCI_OUT_EOF_INT
UHCI_OUT_DONE_INT
UHCI_IN_ERR_EOF_INT
UHCI_IN_SUC_EOF_INT
UHCI_IN_DONE_INT
UHCI_TX_HUNG_INT
UHCI_RX_HUNG_INT
UHCI_TX_START_INT
UHCI_RX_START_INT
382
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
inter-
inter-
inter-
inter-
interrupt.
interrupt. (R/W)
interrupt. (R/W)
interrupt.
interrupt.
interrupt. (R/W)
interrupt. (R/W)
interrupt. (R/W)
interrupt. (R/W)
interrupt. (R/W)
ESP32 TRM (Version 5.2)
0
0 Reset
in-