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Espressif ESP32 Technical Reference Manual

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ESP32

Technical Reference Manual

Version 5.2

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Summary of Contents for Espressif ESP32

Page 1 ESP32 Technical Reference Manual Version 5.2 www.espressif.com...
Page 2 About This Manual The ESP32 Technical Reference Manual is addressed to application developers. The manual provides detailed and complete information on how to use the ESP32 memory and peripherals. For pin definition, electrical characteristics, and package information, please see ESP32 Datasheet.
Page 3 Query Current Interrupt Status of Peripheral Interrupt Source Registers Reset and Clock System Reset 3.1.1 Introduction 3.1.2 Reset Source System Clock 3.2.1 Introduction 3.2.2 Clock Source 3.2.3 CPU Clock 3.2.4 Peripheral Clock 3.2.4.1 APB_CLK Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 4 GPIO Matrix Register Summary 4.12.2 IO MUX Register Summary 4.12.3 RTC IO MUX Register Summary 4.13 Registers 4.13.1 GPIO Matrix Registers 4.13.2 IO MUX Registers 4.13.3 RTC IO MUX Registers DPort Registers Introduction Features Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 5 GP-SPI Interrupt Hardware 7.6.1 SPI Interrupts 7.6.2 DMA Interrupts Register Summary Registers SDIO Slave Controller Overview Features Functional Description 8.3.1 SDIO Slave Block Diagram 8.3.2 Sending and Receiving Data on SDIO Bus Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 6 9.9.3 DMAC Reception Initialization 9.10 SD/MMC Timing 9.11 Clock Phase Selection 9.12 Interrupt 9.13 Register Summary 9.14 Registers 10 Ethernet Media Access Controller (MAC) 10.1 Overview 10.2 EMAC_CORE 10.2.1 Transmit Operation Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 7 11.3 Functional Description 11.3.1 Introduction 11.3.2 Architecture 11.3.3 I2C Bus Timing 11.3.4 I2C cmd Structure 11.3.5 I2C Master Writes to Slave 11.3.6 Master Reads from Slave 11.3.7 Interrupts 11.4 Register Summary Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 8 13.3.7 Flow Control 13.3.7.1 Hardware Flow Control 13.3.7.2 Software Flow Control 13.3.8 UART DMA 13.3.9 UART Interrupts 13.3.10 UHCI Interrupts 13.4 Register Summary 13.4.1 UART Register Summary 13.4.2 UHCI Register Summary Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 9 16.3.2.3 PWM Timer Shadow Register 16.3.2.4 PWM Timer Synchronization and Phase Locking 16.3.3 PWM Operator Submodule 16.3.3.1 PWM Generator Submodule 16.3.3.2 Dead Time Generator Submodule 16.3.3.3 PWM Carrier Submodule 16.3.3.4 Fault Handler Submodule Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 10 Operating Procedure 19.3.1.2 Write Protection 19.3.1.3 Flash Boot Protection 19.3.1.4 Registers 20 eFuse Controller 20.1 Introduction 20.2 Features 20.3 Functional Description 20.3.1 Structure 20.3.1.1 System Parameter efuse_wr_disable 20.3.1.2 System Parameter efuse_rd_disable Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 11 Transmit Interrupt (TXI) 21.5.3.3 Error Warning Interrupt (EWI) 21.5.3.4 Data Overrun Interrupt (DOI) 21.5.3.5 Error Passive Interrupt (TXI) 21.5.3.6 Arbitration Lost Interrupt (ALI) 21.5.3.7 Bus Error Interrupt (BEI) 21.5.4 Transmit and Receive Buffers Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 12 23.3.2 Message Digest 23.3.3 Hash Operation 23.3.4 Speed 23.4 Register Summary 23.5 Registers 24 RSA Accelerator (RSA) 24.1 Introduction 24.2 Features 24.3 Functional Description 24.3.1 Initialization 24.3.2 Large Number Modular Exponentiation Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 13 28.3 Functional Description 28.3.1 Interrupt Identification 28.3.2 Information Recording 28.3.3 Proactive Process Switching 28.4 Register Summary 28.5 Registers 29 On-Chip Sensors and Analog Signal Processing 29.1 Introduction 29.2 Capacitive Touch Sensor Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 14 30.4.8 WAKE – Wake up the Chip 30.4.9 Sleep – Set the ULP Timer’s Wake-up Period 30.4.10 WAIT – Wait for a Number of Cycles 30.4.11 ADC – Take Measurement with ADC 30.4.12 I2C_RD/I2C_WR – Read/Write I²C Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 15 31.3.8 Power-Gating Implementation 31.3.9 Predefined Power Modes 31.3.10 Wakeup Source 31.3.11 Reject Sleep 31.3.12 RTC Timer 31.3.13 RTC Boot 31.4 Register Summary 31.5 Registers Glossary Abbreviations for Peripherals Abbreviations for Registers Revision History Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 16 Transmit Descriptor 2 (TDES2) 10-8 Transmit Descriptor 3 (TDES3) 10-9 Receive Descriptor 0 (RDES0) 10-10 Receive Descriptor 1 (RDES1) 10-11 Receive Descriptor 2 (RDES2) 10-12 Receive Descriptor 3 (RDES3) 10-13 Receive Descriptor 4 (RDES4) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 17 22-3 AES-128 Key Endianness 22-4 AES-192 Key Endianness 22-5 AES-256 Key Endianness 27-1 MPU and MMU Structure for Internal Memory 27-2 MPU for RTC FAST Memory 27-3 MPU for RTC SLOW Memory Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 18 Interrupt Vector Entry Address 28-2 Configuration of PIDCTRL_LEVEL_REG 28-3 Configuration of PIDCTRL_FROM_n_REG 29-1 ESP32 Capacitive Sensing Touch Pads 29-2 Inputs of SAR ADC 29-3 ESP32 SAR ADC Controllers 29-4 Fields of the Pattern Table Register 29-5 Fields of Type I DMA Data Format...
Page 19 IO_MUX, RTC IO_MUX and GPIO Matrix Overview Peripheral Input via IO_MUX, GPIO Matrix Output via GPIO Matrix ESP32 I/O Pad Power Sources (QFN 6*6, Top View) ESP32 I/O Pad Power Sources (QFN 5*5, Top View) DMA Engine Architecture Linked List Structure...
Page 20 12-19 Data Input by I2S DAC Interface 13-1 UART Basic Structure 13-2 UART Shared RAM 13-3 UART Data Frame Structure 13-4 AT_CMD Character Format 13-5 Hardware Flow Control 14-1 LED_PWM Architecture 14-2 LED_PWM High-speed Channel Diagram Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 21 21-2 Various Fields of an Error Frame 21-3 The Bit Fields of an Overload Frame 21-4 The Fields within an Interframe Space 21-5 Layout of a Bit 21-6 TWAI Overview Diagram Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 22 30-20 Sample of a ULP Operation Sequence 30-21 I²C Read Operation 30-22 I²C Write Operation 31-1 ESP32 Power Control 31-2 Digital Core Voltage Regulator 31-3 Low-Power Voltage Regulator 31-4 Flash Voltage Regulator 31-5 Brownout Detector Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 23 List of Figures 31-6 RTC Structure 31-7 RTC Low-Power Clocks 31-8 Digital Low-Power Clocks 31-9 RTC States 31-10 Power Modes 31-11 ESP32 Boot Flow Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 24 1 System and Memory 1.1 Introduction The ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory, external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs. With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning that they use the same addresses to access the same memory.
Page 25 1 System and Memory The block diagram in Figure illustrates the system structure, and the block diagram in Figure illustrates the address map structure. Figure 1-1. System Structure Figure 1-2. System Address Mapping Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 26 KB internal SRAM is divided into three parts: Internal SRAM 0 (192 KB), Internal SRAM 1 (128 KB), and Internal SRAM 2 (200 KB). RTC FAST Memory and RTC SLOW Memory are both implemented as SRAM. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 27 1 System and Memory Table lists all embedded memories and their address ranges on the data and instruction buses. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 28 The capacity of Internal SRAM 0 is 192 KB. Hardware can be configured to use the first 64 KB to cache external memory access. When not used as cache, the first 64 KB can be read and written by either CPU at addresses Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 29 1.3.2.5 Internal SRAM 2 The capacity of Internal SRAM 2 is 200 KB. It can be read and written by either CPU at addresses 0x3FFA_E000 ~ 0x3FFD_FFFF on the data bus. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 30 (in the external memory’s address space), according to the MMU settings. Due to this address mapping, the ESP32 can address up to 16 MB External Flash and 8 MB External SRAM. Table 1-4. External Memory Address Mapping...
Page 31 Read 1.3.4 Cache As shown in Figure 1-3, each of the two CPUs in ESP32 has 32 KB of cache featuring a block size of 32 bytes for accessing external storage. PRO CPU uses bit PRO_CACHE_ENABLE in register DPORT_PRO_CACHE_CTRL_REG to enable the Cache, while APP CPU uses bit APP_CACHE_ENABLE in register DPORT_APP_CACHE_CTRL_REG to enable the same function.
Page 32 Afterwards, the system hardware will set bit x_CACHE_FLUSH_DONE to 1, where can be ”PRO” or ”APP”, indicating that the cache flush operation has been completed. For more information about the address mapping of ESP32 Cache, please refer to Embedded Memory External Memory.
Page 33 On the other hand, using AHB address to read FIFO registers will cause unpredictable errors. To address above issues please strictly follow the instructions documented in ESP32 ECO and Workarounds for Bugs, specifically sections 3.3, 3.10, 3.16, and 3.17.
Page 34 DMA uses the APB_CLK to access memory. Internally, the SRAM is organized in 32K-sized banks. Each CPU and DMA channel can simultaneously access the SRAM at full speed, provided they access addresses in different memory banks. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 35 2.3 Functional Description 2.3.1 Peripheral Interrupt Source ESP32 has 71 peripheral interrupt sources in total. All peripheral interrupt sources are listed in table 2-1. 67 of 71 ESP32 peripheral interrupt sources can be allocated to either CPU. The four remaining peripheral interrupt sources are CPU-specific, two per CPU. GPIO_INTERRUPT_PRO and GPIO_INTERRUPT_PRO_NMI can only be allocated to PRO_CPU.
Page 36 Table 2-1. PRO_CPU, APP_CPU Interrupt Configuration PRO_CPU APP_CPU Peripheral Interrupt Source Peripheral Interrupt Peripheral Interrupt Status Register Status Register Configuration Register Name Configuration Register Name Name DPORT_PRO_MAC_INTR_MAP_REG MAC_INTR DPORT_APP_MAC_INTR_MAP_REG DPORT_PRO_MAC_NMI_MAP_REG MAC_NMI DPORT_APP_MAC_NMI_MAP_REG DPORT_PRO_BB_INT_MAP_REG BB_INT DPORT_APP_BB_INT_MAP_REG DPORT_PRO_BT_MAC_INT_MAP_REG BT_MAC_INT DPORT_APP_BT_MAC_INT_MAP_REG DPORT_PRO_BT_BB_INT_MAP_REG BT_BB_INT DPORT_APP_BT_BB_INT_MAP_REG DPORT_PRO_BT_BB_NMI_MAP_REG BT_BB_NMI...
Page 37 PRO_CPU APP_CPU Peripheral Interrupt Source Peripheral Interrupt Peripheral Interrupt Status Register Status Register Configuration Register Name Configuration Register Name Name DPORT_PRO_SPI2_DMA_INT_MAP_REG SPI2_DMA_INT DPORT_APP_SPI2_DMA_INT_MAP_REG DPORT_PRO_SPI3_DMA_INT_MAP_REG SPI3_DMA_INT DPORT_APP_SPI3_DMA_INT_MAP_REG DPORT_PRO_WDG_INT_MAP_REG WDG_INT DPORT_APP_WDG_INT_MAP_REG DPORT_PRO_TIMER_INT1_MAP_REG TIMER_INT1 DPORT_APP_TIMER_INT1_MAP_REG DPORT_PRO_TIMER_INT2_MAP_REG TIMER_INT2 DPORT_APP_TIMER_INT2_MAP_REG DPORT_PRO_TG_T0_EDGE_INT_MAP_REG DPORT_PRO_INTR_STATUS_REG_1_REG TG_T0_EDGE_INT DPORT_APP_INTR_STATUS_REG_1_REG DPORT_APP_TG_T0_EDGE_INT_MAP_REG DPORT_PRO_TG_T1_EDGE_INT_MAP_REG TG_T1_EDGE_INT DPORT_APP_TG_T1_EDGE_INT_MAP_REG...
Page 38 2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU In this section: • Source_X stands for any particular peripheral interrupt source. • PRO_X_MAP_REG (or APP_X_MAP_REG) stands for any particular peripheral interrupt configuration reg- Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 39 (APP_INTR_STATUS_REG_n), as shown in the mapping in Table 2-1. 2.4 Registers The interrupt matrix registers are part of the DPORT registers and are described in Section in Chapter 5 DPort Registers. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 40 3 Reset and Clock 3.1 System Reset 3.1.1 Introduction The ESP32 has three reset levels: CPU reset, Core reset, and System reset. None of these reset levels clear the RAM. Figure shows the subsystems included in each reset level. Figure 3-1. System Reset •...
Page 41 3.2 System Clock 3.2.1 Introduction The ESP32 integrates multiple clock sources for the CPU cores, the peripherals and the RTC. These clocks can be configured to meet different requirements. Figure shows the system clock structure. Figure 3-2. System Clock Espressif Systems ESP32 TRM (Version 5.2)
Page 42 3 Reset and Clock 3.2.2 Clock Source The ESP32 can use an external crystal oscillator, an internal PLL or an oscillating circuit as a clock source. Specifically, the clock sources available are: • High Speed Clocks – PLL_CLK is an internal PLL clock with a frequency of 320 MHz or 480 MHz.
Page 43 When CPU_CLK source changes, users need to make sure the REF_TICK frequency remains unchanged by setting a correct divider value. Clock divider registers are shown in Table 3-6. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 44 Wi-Fi and BT to both have entered low-power consumption mode first. For LOW_POWER_CLK, one of RC_SLOW_CLK, RTC_SLOW_CLK, RC_FAST_CLK or XTL_CLK can be selected as the low-power consumption mode clock source for Wi-Fi and BT. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 45 350M Hz < f (sdm2 + xtal Please note that sdm1 and sdm0 are not available on revision0 of ESP32. Please consult the silicon revision in ECO and Workarounds for Bugs in ESP32 for further details. Audio PLL can be manually enabled or disabled via registers RTC_CNTL_PLLA_FORCE_PU and RTC_CNTL_PLLA _FORCE_PD, respectively.
Page 46 SYSCON_XTAL_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK is XTL_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1). (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 47 SYSCON_APLL_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK is APLL_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1). (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 48 3 Reset and Clock Register 3.6. SYSCON_DATE_REG (0x007C) 0x16042000 Reset SYSCON_DATE Chip revision register. For more information see ESP32 Series SoC Errata. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 49 4 IO_MUX and GPIO Matrix (GPIO, IO_MUX) 4.1 Overview The ESP32 chip features 34 physical GPIO pads. Each pad can be used as a general-purpose I/O, or be connected to an internal peripheral signal. The IO_MUX, RTC IO_MUX and the GPIO matrix are responsible for routing signals from the peripherals to GPIO pads.
Page 50 GPIO pad in the GPIO Matrix: • Set the GPIO_FUNCx_OEN_SEL bit in the GPIO_FUNCx_OUT_SEL_CFG register to force the pin’s output state to be determined always by the GPIO_ENABLE_DATA[x] field. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 51 The output signal is routed from the peripheral into the GPIO Matrix. It is then routed into the IO_MUX, which is configured to set the chosen pad to ”GPIO” function. This causes the output GPIO signal to be connected to the pad. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 52 3. Configure the IO_MUX to select the GPIO Matrix. Set the IO_MUX_x_REG register corresponding to GPIO as follows: • Set the function field (MCU_SEL) to the IO_MUX function corresponding to GPIO (this is Function 2—numeric value 2—for all pins). Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 53 18 GPIO pads have low power capabilities (RTC domain) and analog functions which are handled by the RTC subsystem of ESP32. The IO_MUX and GPIO Matrix are not used for these functions; rather, the RTC_MUX is used to redirect the I/O to the RTC subsystem.
Page 54 Pins can have different functions when the ESP32 is in Light-sleep mode. If the SLP_SEL bit in the IO_MUX register for a GPIO pad is set to 1, a different set of registers is used to control the pad when the ESP32 is in Light-sleep mode: Table 4-1.
Page 55 VDET_1 GPIO17 VDET_2 VDD_SDIO 32K_XP GPIO16 Analog pads Pads powered by VDD3P3_CPU Pads powered by VDD_SDIO Pads powered by VDD3P3_RTC Figure 4-4. ESP32 I/O Pad Power Sources (QFN 6*6, Top View) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 56 Pads powered by VDD_SDIO Pads powered by VDD3P3_RTC Figure 4-5. ESP32 I/O Pad Power Sources (QFN 5*5, Top View) • Pads marked blue are RTC pads that have their individual analog function and can also act as normal digital IO pads. For details, please see Section 4.11.
Page 57 I2S0I_BCK_out I2S0I_WS_in I2S0I_WS_out I2CEXT0_SCL_in I2CEXT0_SCL_out I2CEXT0_SDA_in I2CEXT0_SDA_out pwm0_sync0_in sdio_tohost_int_out pwm0_sync1_in pwm0_out0a pwm0_sync2_in pwm0_out0b pwm0_f0_in pwm0_out1a pwm0_f1_in pwm0_out1b pwm0_f2_in pwm0_out2a pwm0_out2b pcnt_sig_ch0_in0 pcnt_sig_ch1_in0 pcnt_ctrl_ch0_in0 pcnt_ctrl_ch1_in0 pcnt_sig_ch0_in1 pcnt_sig_ch1_in1 pcnt_ctrl_ch0_in1 pcnt_ctrl_ch1_in1 pcnt_sig_ch0_in2 pcnt_sig_ch1_in2 pcnt_ctrl_ch0_in2 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 58 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 59 I2S0I_DATA_in0 I2S0O_DATA_out0 I2S0I_DATA_in1 I2S0O_DATA_out1 I2S0I_DATA_in2 I2S0O_DATA_out2 I2S0I_DATA_in3 I2S0O_DATA_out3 I2S0I_DATA_in4 I2S0O_DATA_out4 I2S0I_DATA_in5 I2S0O_DATA_out5 I2S0I_DATA_in6 I2S0O_DATA_out6 I2S0I_DATA_in7 I2S0O_DATA_out7 I2S0I_DATA_in8 I2S0O_DATA_out8 I2S0I_DATA_in9 I2S0O_DATA_out9 I2S0I_DATA_in10 I2S0O_DATA_out10 I2S0I_DATA_in11 I2S0O_DATA_out11 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 60 I2S1I_DATA_in7 I2S1O_DATA_out7 I2S1I_DATA_in8 I2S1O_DATA_out8 I2S1I_DATA_in9 I2S1O_DATA_out9 I2S1I_DATA_in10 I2S1O_DATA_out10 I2S1I_DATA_in11 I2S1O_DATA_out11 I2S1I_DATA_in12 I2S1O_DATA_out12 I2S1I_DATA_in13 I2S1O_DATA_out13 I2S1I_DATA_in14 I2S1O_DATA_out14 I2S1I_DATA_in15 I2S1O_DATA_out15 I2S1O_DATA_out16 I2S1O_DATA_out17 I2S1O_DATA_out18 I2S1O_DATA_out19 I2S1O_DATA_out20 I2S1O_DATA_out21 I2S1O_DATA_out22 I2S1O_DATA_out23 I2S0I_H_SYNC I2S0I_V_SYNC I2S0I_H_ENABLE I2S1I_H_SYNC I2S1I_V_SYNC Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 61 EMAC_RX_CLK SD_CLK SD_CLK SPICLK GPIO6 HS1_CLK U1CTS SD_DATA_0 SD_DATA0 SPIQ GPIO7 HS1_DATA0 U2RTS SD_DATA_1 SD_DATA1 SPID GPIO8 HS1_DATA1 U2CTS SD_DATA_2 SD_DATA2 SPIHD GPIO9 HS1_DATA2 U1RXD SD_DATA_3 SD_DATA3 SPIWP GPIO10 HS1_DATA3 U1TXD Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 62 • R - Pad has RTC/analog functions via RTC_MUX. • I - Pad can only be configured as input GPIO. These input-only pads do not feature an output driver or internal pull-up/pull-down circuitry. Please refer to the ESP32 Pin Lists in ESP32 Datasheet for more details.
Page 63 GPIO 0-31 input register 0x3FF4403C GPIO_IN1_REG GPIO 32-39 input register 0x3FF44040 GPIO_STATUS_REG GPIO 0-31 interrupt status register 0x3FF44044 GPIO_STATUS_W1TS_REG GPIO 0-31 interrupt status register_W1TS 0x3FF44048 GPIO_STATUS_W1TC_REG GPIO 0-31 interrupt status register_W1TC 0x3FF4404C Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 64 Configuration register for pad GPIO39 0x3FF49010 IO_MUX_GPIO34_REG Configuration register for pad GPIO34 0x3FF49014 IO_MUX_GPIO35_REG Configuration register for pad GPIO35 0x3FF49018 IO_MUX_GPIO32_REG Configuration register for pad GPIO32 0x3FF4901C IO_MUX_GPIO33_REG Configuration register for pad GPIO33 0x3FF49020 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 65 IO_MUX_GPIO23_REG Configuration register for pad GPIO23 0x3FF4908C IO_MUX_GPIO24_REG Configuration register for pad GPIO24 0x3FF49090 1. GPIO20 is only available for ESP32-PICO-V3 and ESP32-PICO-V3-02. Please refer to ESP32-PICO Series Datasheet for more information. 4.12.3 RTC IO MUX Register Summary Name Description...
Page 66 The addresses in parenthesis besides register names are the register addresses relative to the GPIO base ad- dress provided in Table Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 4.12.1 GPIO Matrix Register Summary. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 67 GPIO_OUT_W1TC_REG GPIO0-31 output clear register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_OUT_REG will be cleared. (WO) Register 4.4. GPIO_OUT1_REG (0x0010) Reset GPIO_OUT_DATA GPIO32-39 output value. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 68 Register 4.8. GPIO_ENABLE_W1TS_REG (0x0024) Reset GPIO_ENABLE_W1TS_REG GPIO0-31 output enable set register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_ENABLE will be set. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 69 Register 4.12. GPIO_ENABLE1_W1TC_REG (0x0034) Reset GPIO_ENABLE_DATA GPIO32-39 output enable clear register. For every bit that is 1 in the value written here, the corresponding bit in GPIO_ENABLE1 will be cleared. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 70 GPIO_STATUS_INT GPIO0-31 interrupt status register. Each bit can be either of the two interrupt sources for the two CPUs. The enable bits in GPIO_PINn_INT_ENA, corresponding to the 13-16 bits in GPIO_PINn_REG should be set to 1. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 71 GPIO_STATUS1_INT GPIO32-39 interrupt status register. Each bit can be either of the two interrupt sources for the two CPUs. The enable bits in GPIO_PINn_INT_ENA, corresponding to the 13-16 bits in GPIO_PINn_REG should be set to 1. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 72 GPIO_STATUS1_INT will be cleared. (WO) Register 4.22. GPIO_ACPU_INT_REG (0x0060) Reset GPIO_ACPU_INT_REG GPIO0-31 APP CPU interrupt status. (RO) Register 4.23. GPIO_ACPU_NMI_INT_REG (0x0064) Reset GPIO_ACPU_NMI_INT_REG GPIO0-31 APP CPU non-maskable interrupt status. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 73 GPIO_PCPU_NMI_INT_REG GPIO0-31 PRO CPU non-maskable interrupt status. (RO) Register 4.26. GPIO_ACPU_INT1_REG (0x0074) Reset GPIO_APPCPU_INT GPIO32-39 APP CPU interrupt status. (RO) Register 4.27. GPIO_ACPU_NMI_INT1_REG (0x0078) Reset GPIO_APPCPU_NMI_INT GPIO32-39 APP CPU non-maskable interrupt status. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 74 4 IO_MUX and GPIO Matrix (GPIO, IO_MUX) Register 4.28. GPIO_PCPU_INT1_REG (0x007c) Reset GPIO_PROCPU_INT GPIO32-39 PRO CPU interrupt status. (RO) Register 4.29. GPIO_PCPU_NMI_INT1_REG (0x0080) Reset GPIO_PROCPU_NMI_INT GPIO32-39 PRO CPU non-maskable interrupt status. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 75 GPIO_FUNCy_IN_SEL Selection control for peripheral input y. A value of 0-39 selects which of the 40 GPIO Matrix input pins this signal is connected to, or 0x38 for a constantly high input or 0x30 for a constantly low input. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 76 The addresses in parenthesis besides register names are the register addresses relative to the IO MUX base addresses provided in Table Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 4.12.2 IO MUX Register Summary. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 77 • Only the above mentioned combinations of clock source (i.e. I2S0/1_CLK, APLL clock) and clock output pins (i.e. CLK_OUT1 ~ 3) are possible. • The CLK_OUT1 ~ 3 can be found in the IO_MUX Pad Summary. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 78 FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. (R/W) FUN_IE Input enable of the pad.
Page 79 RTCIO_RTC_GPIO_OUT will be set. (WO) Register 4.37. RTCIO_RTC_GPIO_OUT_W1TC_REG (0x0008) Reset RTCIO_RTC_GPIO_OUT_DATA_W1TC GPIO0-17 output clear register. For every bit that is 1 in the value written here, the corresponding bit in RTCIO_RTC_GPIO_OUT will be cleared. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 80 Register 4.40. RTCIO_RTC_GPIO_ENABLE_W1TC_REG (0x0014) Reset RTCIO_RTC_GPIO_ENABLE_W1TC GPIO0-17 output enable clear register. For every bit that is 1 in the value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be cleared. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 81 RTCIO_RTC_GPIO_STATUS_INT will be set. (WO) Register 4.43. RTCIO_RTC_GPIO_STATUS_W1TC_REG (0x0020) Reset RTCIO_RTC_GPIO_STATUS_INT_W1TC GPIO0-17 interrupt clear register. For every bit that is 1 in the value written here, the corresponding bit in RTCIO_RTC_GPIO_STATUS_INT will be cleared. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 82 1 for high level, and 0 for low level. (RO) Register 4.45. RTCIO_RTC_GPIO_PINn_REG (n: 0-17) (0x28+4*n) Reset RTCIO_RTC_GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable. This will only wake up the ESP32 from Light-sleep. (R/W) RTCIO_RTC_GPIO_PINn_INT_TYPE GPIO interrupt type selection. (R/W) 0: GPIO interrupt disable;...
Page 83 Set to 1 to enable the Hold function of pad GPIO22 Bit[16] Set to 1 to enable the Hold function of pad GPIO23 1. GPIO20 is only available for ESP32-PICO-V3 and ESP32-PICO-V3-02. Please refer to ESP32-PICO Series Datasheet for more information. Espressif Systems ESP32 TRM (Version 5.2)
Page 84 RTCIO_SENSOR_SENSEn_SLP_SEL Selection of sleep mode for the pad: set to 1 to put the pad in sleep mode. (R/W) RTCIO_SENSOR_SENSEn_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W) RTCIO_SENSOR_SENSEn_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 85 RTCIO_ADC_ADCn_SLP_SEL Signal selection of pad’s sleep mode. Set this bit to 1 to put the pad to sleep. (R/W) RTCIO_ADC_ADCn_SLP_IE Input enable of the pad in sleep mode. 1 enabled; 0 disabled. (R/W) RTCIO_ADC_ADCn_FUN_IE Input enable of the pad. 1 enabled; 0 disabled. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 86 RTCIO_PAD_PDAC1_FUN_IE Input enable of the pad. 1: enabled it; 0: disabled. (R/W) RTCIO_PAD_PDAC1_DAC_XPD_FORCE Power on DAC1. Usually, we need to tristate PDAC1 if we power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 87 RTCIO_PAD_PDAC2_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W) RTCIO_PAD_PDAC2_DAC_XPD_FORCE Power on DAC2. Usually, we need to tristate PDAC2 if we power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 88 RTCIO_XTAL_X32P_SLP_SEL Sleep mode selection. Set this bit to 1 to put the pad to sleep. (R/W) RTCIO_XTAL_X32P_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 89 RTCIO_TOUCH_DREFH Touch sensor saw wave top voltage. (R/W) RTCIO_TOUCH_DREFL Touch sensor saw wave bottom voltage. (R/W) RTCIO_TOUCH_DRANGE Touch sensor saw wave voltage range. (R/W) RTCIO_TOUCH_DCUR Touch sensor bias current. When BIAS_SLEEP is enabled, this setting is available. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 90 For detailed drive strength, please see ESP32 Datasheet > Appendix A.1 Notes on ESP32 Pin Lists > Note 8. (R/W) RTCIO_TOUCH_PADn_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W) RTCIO_TOUCH_PADn_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W) RTCIO_TOUCH_PADn_DAC Touch sensor slope control.
Page 91 1: The input signal from the touch pad is routed to IO_MUX through analog function. 0: The input signal from the touch pad is routed to IO_MUX through digital function. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 92 RTCIO_EXT_WAKEUP0_SEL GPIO[0-17] can be used to wake up the chip when the chip is in the sleep mode. This register prompts the pad source to wake up the chip when the latter is in deep/light sleep mode. 0: select GPIO0; 1: select GPIO2, etc. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 93 RTCIO_SAR_I2C_SDA_SEL Selects the other pad as the RTC I2C SDA signal. TOUCH_PAD[1]; 1: pad TOUCH_PAD[3]. Default value is 0. (R/W) RTCIO_SAR_I2C_SCL_SEL Selects the other pad as the RTC I2C SCL signal. TOUCH_PAD[0]; 1: pad TOUCH_PAD[2]. Default value is 0. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 94 5 DPort Registers 5.1 Introduction The ESP32 integrates a large number of peripherals, and enables the control of individual peripherals to achieve optimal characteristics in performance-vs-power-consumption scenarios. The DPort registers control clock management (clock gating), power management, and the configuration of peripherals and core-system mod- ules.
Page 95 • Reset registers cannot be cleared by hardware. Therefore, SW reset clear is required after setting the reset registers. • ESP32 features low power consumption. This is why some peripheral clocks are gated (disabled) by default. Before using any of these peripherals, it is mandatory to enable the clock for the given periph- eral by setting the corresponding CLK_EN bit to 1, and release the peripheral from reset state to make it operational by setting the RST_EN bit to 0.
Page 96 0x3FF00144 DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF00148 DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF0014C DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00150 DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00154 DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF00158 DPORT_PRO_GPIO_INTERRUPT_MAP_REG interrupt map 0x3FF0015C DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG interrupt map 0x3FF00160 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 97 0x3FF001F8 DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG interrupt map 0x3FF001FC DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG interrupt map 0x3FF00200 DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF00204 DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF00208 DPORT_PRO_MMU_IA_INT_MAP_REG interrupt map 0x3FF0020C DPORT_PRO_MPU_IA_INT_MAP_REG interrupt map 0x3FF00210 DPORT_PRO_CACHE_IA_INT_MAP_REG interrupt map 0x3FF00214 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 98 0x3FF002A4 DPORT_APP_UART2_INTR_MAP_REG interrupt map 0x3FF002A8 DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG interrupt map 0x3FF002AC DPORT_APP_EMAC_INT_MAP_REG interrupt map 0x3FF002B0 DPORT_APP_PWM0_INTR_MAP_REG interrupt map 0x3FF002B4 DPORT_APP_PWM1_INTR_MAP_REG interrupt map 0x3FF002B8 DPORT_APP_LEDC_INT_MAP_REG interrupt map 0x3FF002C4 DPORT_APP_EFUSE_INT_MAP_REG interrupt map 0x3FF002C8 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 99 MMU for the DPORT_IMMU_PAGE_MODE_REG 0x3FF00080 internal SRAM 0 page size in the MMU for the DPORT_DMMU_PAGE_MODE_REG 0x3FF00084 internal SRAM 2 DPORT_AHB_MPU_TABLE_0_REG MPU for configuring DMA 0x3FF000B4 DPORT_AHB_MPU_TABLE_1_REG MPU for configuring DMA 0x3FF000B8 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 100 DPORT_IMMU_TABLE1_REG 0x3FF00508 SRAM 0 MMU register 1 for Internal DPORT_IMMU_TABLE2_REG 0x3FF0050C SRAM 0 MMU register 1 for internal DPORT_IMMU_TABLE3_REG 0x3FF00510 SRAM 0 MMU register 1 for internal DPORT_IMMU_TABLE4_REG 0x3FF00514 SRAM 0 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 101 DPORT_DMMU_TABLE7_REG 0x3FF00560 SRAM 2 MMU register 1 for internal DPORT_DMMU_TABLE8_REG 0x3FF00564 SRAM 2 MMU register 1 for internal DPORT_DMMU_TABLE9_REG 0x3FF00568 SRAM 2 MMU register 1 for internal DPORT_DMMU_TABLE10_REG 0x3FF0056C SRAM 2 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 102 0x3FF0001C DPORT_PERI_RST_EN_REG reset for peripherals 0x3FF00020 DPORT_PERIP_CLK_EN_REG clock gate for peripherals 0x3FF000C0 DPORT_PERIP_RST_EN_REG reset for peripherals 0x3FF000C4 DPORT_WIFI_CLK_EN_REG clock gate for Wi-Fi 0x3FF000CC DPORT_WIFI_RST_EN_REG reset for Wi-Fi 0x3FF000D0 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 103 DPORT_PERI_EN_SHA Set the bit to enable the clock of SHA module. Clear the bit to disable the clock of SHA module. (R/W) DPORT_PERI_EN_AES Set the bit to enable the clock of AES module. Clear the bit to disable the clock of AES module. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 104 DPORT_APPCPU_RESETTING Set to 1 to reset APP_CPU. Clear the bit to release APP_CPU. (R/W) Register 5.6. DPORT_APPCPU_CTRL_REG_B_REG (0x030) Reset DPORT_APPCPU_CLKGATE_EN Set to 1 to enable the clock of APP_CPU. Clear the bit to disable the clock of APP_CPU. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 105 DPORT_APPCPU_CTRL_REG_D_REG When APP_CPU is booted up with ROM code, it will jump to the address stored in this register. (R/W) Register 5.9. DPORT_CPU_PER_CONF_REG (0x03C) Reset DPORT_CPU_CPUPERIOD_SEL Select CPU clock. Refer to Table for details. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 106 DPORT_PRO_DRAM_SPLIT Determines the virtual address mode of the external SRAM. (R/W) DPORT_PRO_SINGLE_IRAM_ENA Determines a special mode for PRO_CPU access to the external flash. (R/W) DPORT_PRO_CACHE_FLUSH_DONE PRO_CPU cache-flush done. (RO) DPORT_PRO_CACHE_FLUSH_ENA Flushes the PRO_CPU cache. (R/W) DPORT_PRO_CACHE_ENABLE Enables the PRO_CPU cache. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 107 0: Enable (R/W) DPORT_PRO_CACHE_MASK_IRAM1 Disables access from PRO_CPU IRAM1 to PRO cache. 1: Disable 0: Enable (R/W) DPORT_PRO_CACHE_MASK_IRAM0 Disables access from PRO_CPU IRAM0 to PRO cache. 1: Disable 0: Enable (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 108 DPORT_APP_DRAM_SPLIT Determines the virtual address mode of the External SRAM. (R/W) DPORT_APP_SINGLE_IRAM_ENA Determines a special mode for APP_CPU access to the external flash. (R/W) DPORT_APP_CACHE_FLUSH_DONE APP_CPU cache-flush done. (RO) DPORT_APP_CACHE_FLUSH_ENA Flushes the APP_CPU cache. (R/W) DPORT_APP_CACHE_ENABLE Enables the APP_CPU cache. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 109 0: Enable (R/W) DPORT_APP_CACHE_MASK_IRAM1 Disables access from APP_CPU IRAM1 to APP cache. 1: Disable 0: Enable (R/W) DPORT_APP_CACHE_MASK_IRAM0 Disables access from APP_CPU IRAM0 to APP cache. 1: Disable 0: Enable (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 110 DPORT_IMMU_PAGE_MODE Page size in the MMU for the internal SRAM 0. (R/W) Register 5.16. DPORT_DMMU_PAGE_MODE_REG (0x084) Reset DPORT_DMMU_PAGE_MODE Page size in the MMU for the internal SRAM 2. (R/W) Register 5.17. DPORT_AHB_MPU_TABLE_0_REG (0x0B4) 0xFFFFFFFF Reset DPORT_AHB_MPU_TABLE_0_REG MPU for DMA. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 111 5 DPort Registers Register 5.18. DPORT_AHB_MPU_TABLE_1_REG (0x0B8) 0x1FF Reset DPORT_AHB_ACCESS_GRANT_1 MPU for DMA. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 112 DPORT_UHCI1_CLK_EN UDMA1 module. (R/W) DPORT_LEDC_CLK_EN LEDC module. (R/W) DPORT_PCNT_CLK_EN PCNT module. (R/W) DPORT_RMT_CLK_EN RMT module. (R/W) DPORT_UHCI0_CLK_EN UDMA0 module. (R/W) DPORT_I2C_EXT0_CLK_EN I2C0 module. (R/W) DPORT_SPI2_CLK_EN SPI2 module. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 113 SD/MMC module. (R/W) DPORT_WIFI_CLK_SDIOSLAVE_EN Set the bit to enable the clock of SDIO module. Clear the bit to disable the clock of SDIO module. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 114 Interrupt in both CPUs. (R/W) Register 5.24. DPORT_PRO_INTR_STATUS_REG_n_REG (n: 0-2) (0xEC+4*n) 0x000000000 Reset DPORT_PRO_INTR_STATUS_REG_n_REG PRO_CPU interrupt status. (RO) Register 5.25. DPORT_APP_INTR_STATUS_REG_n_REG (n: 0-2) (0xF8+4*n) 0x000000000 Reset DPORT_APP_INTR_STATUS_REG_n_REG APP_CPU interrupt status. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 115 Register 5.53. DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (0x170) Register 5.54. DPORT_PRO_SPI_INTR_0_MAP_REG (0x174) Register 5.55. DPORT_PRO_SPI_INTR_1_MAP_REG (0x178) Register 5.56. DPORT_PRO_SPI_INTR_2_MAP_REG (0x17C) Register 5.57. DPORT_PRO_SPI_INTR_3_MAP_REG (0x180) Register 5.58. DPORT_PRO_I2S0_INT_MAP_REG (0x184) Register 5.59. DPORT_PRO_I2S1_INT_MAP_REG (0x188) Register 5.60. DPORT_PRO_UART_INTR_MAP_REG (0x18C) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 116 Register 5.84. DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (0x1F4) Register 5.85. DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (0x1F8) Register 5.86. DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (0x1FC) Register 5.87. DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (0x200) Register 5.88. DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (0x204) Register 5.89. DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (0x208) Register 5.90. DPORT_PRO_MMU_IA_INT_MAP_REG (0x20C) Register 5.91. DPORT_PRO_MPU_IA_INT_MAP_REG (0x210) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 117 Register 5.111. DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG (0x260) Register 5.112. DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG (0x264) Register 5.113. DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG (0x268) Register 5.114. DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG (0x26C) Register 5.115. DPORT_APP_GPIO_INTERRUPT_MAP_REG (0x270) Register 5.116. DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG (0x274) Register 5.117. DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG (0x278) Register 5.118. DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG (0x27C) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 118 Register 5.146. DPORT_APP_WDG_INT_MAP_REG (0x2F4) Register 5.147. DPORT_APP_TIMER_INT1_MAP_REG (0x2F8) Register 5.148. DPORT_APP_TIMER_INT2_MAP_REG (0x2FC) Register 5.149. DPORT_APP_TG_T0_EDGE_INT_MAP_REG (0x300) Register 5.150. DPORT_APP_TG_T1_EDGE_INT_MAP_REG (0x304) Register 5.151. DPORT_APP_TG_WDT_EDGE_INT_MAP_REG (0x308) Register 5.152. DPORT_APP_TG_LACT_EDGE_INT_MAP_REG (0x30C) Register 5.153. DPORT_APP_TG1_T0_EDGE_INT_MAP_REG (0x310) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 119 Register 5.173. DPORT_AHBLITE_MPU_TABLE_RMT_REG (0x380) Register 5.174. DPORT_AHBLITE_MPU_TABLE_PCNT_REG (0x384) Register 5.175. DPORT_AHBLITE_MPU_TABLE_SLC_REG (0x388) Register 5.176. DPORT_AHBLITE_MPU_TABLE_LEDC_REG (0x38C) Register 5.177. DPORT_AHBLITE_MPU_TABLE_EFUSE_REG (0x390) Register 5.178. DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG (0x394) Register 5.179. DPORT_AHBLITE_MPU_TABLE_PWM0_REG (0x39C) Register 5.180. DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG (0x3A0) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 120 MMU for internal SRAM. When is 0 ~ 9, the reset value is 0. When is 10 ~ 15, the reset value is 10, 11, 12, 13, 14, 15, respectively. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 121 0 ~ 15, the reset value is 0 ~ 15, respec- tively. (R/W) Register 5.194. DPORT_SPI_DMA_CHAN_SEL_REG (0x5A8) Reset DPORT_SPI_SPI3_DMA_CHAN_SEL Selects DMA channel for SPI3. (R/W) DPORT_SPI_SPI2_DMA_CHAN_SEL Selects DMA channel for SPI2. (R/W) DPORT_SPI_SPI1_DMA_CHAN_SEL Selects DMA channel for SPI1. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 122 Data can be quickly moved with DMA without any CPU intervention, thus allowing for more efficient use of the cores when processing data. In the ESP32, 13 peripherals are capable of using DMA for data transfer, namely, UART0, UART1, UART2, SPI1, SPI2, SPI3, I2S0, I2S1, SDIO slave, SD/MMC host, EMAC, BT, and Wi-Fi.
Page 123 This enables the DMA engine to be used for transferring an arbitrary number of data bytes. 6.4 UART DMA (UDMA) The ESP32 has three UART interfaces that share two UDMA (UART DMA) controllers. The UHCI_UARTx_CE is 0, 1, or 2) is used for selecting the UART controller to use the UDMA. Espressif Systems ESP32 TRM (Version 5.2)
Page 124 Please note that the buffer address pointer field in in_link descriptors should be word-aligned, and the size field in the last in_link descriptor should be at least 4 bytes larger than the length of received data. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 125 Figure 6-4. SPI DMA ESP32 SPI modules can use DMA as well as the CPU for data exchange with peripherals. As can be seen from Figure 6-4, two DMA channels are shared by SPI1, SPI2 and SPI3 controllers. Each DMA channel can be used by any one SPI controller at any given time.
Page 126 6 DMA Controller (DMA) 6.6 I2S DMA Interface The ESP32 integrates two I2S modules, I2S0 and I2S1, each of which is powered by a DMA channel. The REG_I2S_DSCR_EN bit in I2S_FIFO_CONF_REG is used for enabling the DMA operation. ESP32 I2S DMA uses the standard linked-list descriptor to configure DMA operations for data transfer.
Page 127 Figure 7-1. SPI Architecture As Figure shows, ESP32 integrates four SPI controllers which can be used to communicate with external devices that use the SPI protocol. Controller SPI0 is used as a buffer for accessing external memory. Controller SPI1 can be used as a master. Controllers SPI2 and SPI3 can be configured as either a master or a slave. When used as a master, each SPI controller can drive multiple CS signals (CS0~CS2) to activate multiple slaves.
Page 128 Every SPI master can be connected to three slaves at most by default. When not using DMA, the maximum length of data received/sent in one burst is 64 bytes. The data length is in multiples of one byte. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 129 MISO. 7.3.1 GP-SPI Four-line Full-duplex Communication When configured to four-line full-duplex mode, the ESP32 SPI can act as either a master or a slave. The length of received and sent data needs to be set by configuring the SPI_MISO_DLEN_REG, SPI_MOSI_DLEN_REG registers for master mode as well as SPI_SLV_RDBUF_DLEN_REG, SPI_SLV_WRBUF_DLEN_REG registers for slave mode.
Page 130 ”received data + sent data” are not applicable to DMA. • When ESP32 SPI acts as a slave, the master CS should be active at least one SPI clock period before a read/write process is initiated, and should be inactive at least one SPI clock period after the read/write process is com- pleted.
Page 131 ESP32 SPI master and slave, respectively. Note that for mode0 and mode2 in Table 7-4, the registers are configured differently in non-DMA mode and DMA mode, and that the SPI slave data is output in advance in DMA mode.
Page 132 SPI clock and is sampled on the rising edge. 7.4.2 GP-SPI Timing The data signals of ESP32 GP-SPI can be mapped to physical pins either via IO_MUX or via IO_MUX and GPIO matrix. Input signals will be delayed by two clk clock cycles when they pass through the matrix.
Page 133 To support communication with special slave devices, ESP32 QSPI implements a specifically designed com- munication protocol. The communication format of ESP32 QSPI master is the same as that of GP-SPI four-line half-duplex communication, except that in address phase and data phase, software can configure registers to enable two-line or four-line transmission.
Page 134 Note that GPI-SPI full-duplex mode does not support dummy phase. 7.6 GP-SPI Interrupt Hardware ESP32 SPI generates two types of interrupts. One is the SPI interrupt and the other is the SPI DMA inter- rupt. ESP32 SPI reckons the completion of send- and/or receive-operations as the completion of one operation from the controller and generates one interrupt.
Page 135 3FF43024 3FF42024 3FF64024 3FF65024 R/W tion SPI_MOSI_DLEN_REG MOSI length 3FF43028 3FF42028 3FF64028 3FF65028 R/W SPI_W0_REG SPI data register 0 3FF43080 3FF42080 3FF64080 3FF65080 R/W SPI_W1_REG SPI data register 1 3FF43084 3FF42084 3FF64084 3FF65084 R/W Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 136 EOF occurs Current descriptor SPI_OUTLINK_DSCR_REG 3FF4313C 3FF4213C 3FF6413C 3FF6513C RO pointer Next descriptor data SPI_OUTLINK_DSCR_BF0_REG 3FF43140 3FF42140 3FF64140 3FF65140 RO pointer Current descriptor SPI_OUTLINK_DSCR_BF1_REG 3FF43144 3FF42144 3FF64144 3FF65144 RO data pointer Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 137 Raw interrupt status 3FF43114 3FF42114 3FF64114 3FF65114 Masked interrupt sta- SPI_DMA_INT_ST_REG 3FF43118 3FF42118 3FF64118 3FF65118 SPI_DMA_INT_ENA_REG Interrupt enable bits 3FF43110 3FF42110 3FF64110 3FF65110 SPI_DMA_INT_CLR_REG Interrupt clear bits 3FF4311C 3FF4211C 3FF6411C 3FF6511C Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 138 If the address length is smaller than 33 bits, this register stores all the address value. The register is in valid only when SPI_USR_ADDR bit is set to 1. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 139 SPI_FREAD_QUAD This bit is used to enable four-line data reads in QSPI mode. (R/W) SPI_FREAD_DUAL This bit is used to enable two-line data reads in QSPI mode. (R/W) SPI_FASTRD_MODE Reserved. Register 7.4. SPI_CTRL1_REG (0xC) 0x05 Reset SPI_CS_HOLD_DELAY Reserved. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 140 7 SPI Controller (SPI) Register 7.5. SPI_RD_STATUS_REG (0x10) 0x000 0x000 Reset SPI_STATUS_EXT Reserved. SPI_STATUS Reserved. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 141 SPI_SETUP_TIME It is to configure the time between the CS signal active edge and the first SPI clock edge. It is only valid in half-duplex mode or QSPI mode and when SPI_CS_SETUP is set to 1. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 142 SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W) SPI_CLKCNT_L In master mode, it is equal to SPI_CLKCNT_N. It is only valid when SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 143 SPI_CK_I_EDGE In slave mode, the bit is the same as SPI_CK_OUT_EDGE in master mode. It is combined with SPI_MISO_DELAY_MODE. It is only valid in slave mode. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 144 SPI_USR_DUMMY_CYCLELEN It indicates the number of SPI clock cycles for the dummy phase minus one in SPI half-duplex mode and QSPI mode. It is only valid when SPI_USR_DUMMY is set to 1. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 145 0x0000000 Reset SPI_USR_MISO_DBITLEN It indicates the length of MISO data minus one, in multiples of one bit. It is only valid when SPI_USR_MISO is set to 1 in master mode. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 146 SPI_CS2_DIS This bit enables the SPI CS2 signal. 1: disables CS2; 0: enables CS2. (R/W) SPI_CS1_DIS This bit enables the SPI CS1 signal. 1: disables CS1; 0: enables CS1. (R/W) SPI_CS0_DIS This bit enables the SPI CS0 signal. 1: disables CS0; 0: enables CS0. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 147 SPI_SLV_RD_STA_DONE The raw interrupt status bit for the SPI_SLV_RD_STA_INT interrupt. It is set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 148 It is only valid in slave half-duplex mode. (R/W) SPI_SLV_RDBUF_DUMMY_EN In slave mode, this bit enables the dummy phase for read-buffer op- erations. It is only valid in slave half-duplex mode. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 149 It is only valid when SPI_SLV_RDSTA_DUMMY_EN is set to 1 in slave half-duplex mode. (R/W) Register 7.18. SPI_SLAVE3_REG (0x44) Reset SPI_SLV_WRSTA_CMD_VALUE Reserved. SPI_SLV_RDSTA_CMD_VALUE Reserved. SPI_SLV_WRBUF_CMD_VALUE Reserved. SPI_SLV_RDBUF_CMD_VALUE Reserved. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 150 SPI_SLV_RDATA_BIT It indicates the bit length of data the master reads from the slave, minus one. It is only valid in slave half-duplex mode. (R/W) Register 7.22. SPI_Wn_REG (n: 0-15) (0x80+4*n) Reset SPI_Wn_REG Data buffer. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 151 SPI_ST The current state of the SPI state machine: (RO) 0: idle state 1: preparation state 2: send command state 3: send data state 4: read data state 5: write data state 6: wait state 7: done state Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 152 SPI_OUTLINK_START Set the bit to start to use outlink descriptor. (R/W) SPI_OUTLINK_STOP Set the bit to stop to use outlink descriptor. (R/W) SPI_OUTLINK_ADDR The address of the first outlink descriptor. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 153 (R/W) SPI_INLINK_ADDR The address of the first inlink descriptor. (R/W) Register 7.28. SPI_DMA_STATUS_REG (0x10C) Reset SPI_DMA_TX_EN SPI DMA write-data status bit. (RO) SPI_DMA_RX_EN SPI DMA read-data status bit. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 154 SPI_IN_DONE_INT_ENA The interrupt enable bit for the SPI_IN_DONE_INT interrupt. (R/W) SPI_INLINK_DSCR_ERROR_INT_ENA The interrupt enable SPI_INLINK_DSCR_ERROR_INT interrupt. (R/W) SPI_OUTLINK_DSCR_ERROR_INT_ENA The interrupt enable SPI_OUTLINK_DSCR_ERROR_INT interrupt. (R/W) SPI_INLINK_DSCR_EMPTY_INT_ENA The interrupt enable SPI_INLINK_DSCR_EMPTY_INT interrupt. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 155 SPI_IN_DONE_INT_RAW The raw interrupt status bit for the SPI_IN_DONE_INT interrupt. (RO) SPI_INLINK_DSCR_ERROR_INT_RAW The interrupt status SPI_INLINK_DSCR_ERROR_INT interrupt. (RO) SPI_OUTLINK_DSCR_ERROR_INT_RAW The interrupt status SPI_OUTLINK_DSCR_ERROR_INT interrupt. (RO) SPI_INLINK_DSCR_EMPTY_INT_RAW The interrupt status SPI_INLINK_DSCR_EMPTY_INT interrupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 156 SPI_IN_DONE_INT_ST The masked interrupt status bit for the SPI_IN_DONE_INT interrupt. (RO) SPI_INLINK_DSCR_ERROR_INT_ST The masked interrupt status SPI_INLINK_DSCR_ERROR_INT interrupt. (RO) SPI_OUTLINK_DSCR_ERROR_INT_ST The masked interrupt status SPI_OUTLINK_DSCR_ERROR_INT interrupt. (RO) SPI_INLINK_DSCR_EMPTY_INT_ST The masked interrupt status SPI_INLINK_DSCR_EMPTY_INT interrupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 157 SPI_IN_ERR_EOF_DES_ADDR_REG The inlink descriptor address when SPI DMA encountered an error in receiving data. (RO) Register 7.34. SPI_IN_SUC_EOF_DES_ADDR_REG (0x124) Reset SPI_IN_SUC_EOF_DES_ADDR_REG The last inlink descriptor address when SPI DMA encountered EOF. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 158 Reset SPI_OUT_EOF_BFR_DES_ADDR_REG The buffer address corresponding to the outlink descriptor that produces EOF. (RO) Register 7.39. SPI_OUT_EOF_DES_ADDR_REG (0x138) Reset SPI_OUT_EOF_DES_ADDR_REG The last outlink descriptor address when SPI DMA encountered EOF. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 159 Register 7.43. SPI_DMA_RSTATUS_REG (0x148) Reset TX_FIFO_EMPTY The SPI DMA TX FIFO is empty. (RO) TX_FIFO_FULL The SPI DMA TX FIFO is full. (RO) TX_DES_ADDRESS The LSB of the SPI DMA outlink descriptor address. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 160 Register 7.44. SPI_DMA_TSTATUS_REG (0x14C) Reset RX_FIFO_EMPTY The SPI DMA RX FIFO is empty. (RO) RX_FIFO_FULL The SPI DMA RX FIFO is full. (RO) RX_DES_ADDRESS The LSB of the SPI DMA inlink descriptor address. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 161 SD Input/Output (SDIO) Specification Version 2.0. This allows a host controller to access the ESP32 via an SDIO bus protocol, enabling high-speed data transfer. The SDIO interface may be used to read ESP32 SDIO registers directly and access shared memory via Direct Memory Access (DMA), thus reducing processing overhead while maintaining high performance.
Page 162 Function1 in the Slave, according to the SDIO protocol, data transmission will begin. ESP32 segregates data into packets sent to/from the Host. To achieve high bus utilization and data transfer rates, we recommend the single block transmission mode. For detailed information on this mode, please refer to the SDIO V2.0 protocol specification.
Page 163 The Slave’s linked-list chain is shown in Figure 8-5: Figure 8-5. SDIO Slave Linked List 8.3.5 Packet-Sending/-Receiving Procedure The SDIO Host and Slave devices need to follow specific data transfer procedures to successfully exchange data over the SDIO interface. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 164 • SLCHOST_PKT_LEN: Packet length accumulator register. The current value minus the value of last time equals the packet length sent this time. In order to start DMA, the CPU needs to write the low 20 bits of the address of the first linked-list element to Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 165 If the buffers are not enough, the Host needs to constantly poll the register until there are enough buffers available. To ensure sufficient receiving buffers, the Slave CPU must constantly load buffers on the receiving linked list. The process is shown in Figure 8-8. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 166 SLCHOST_FRC_POS_SAMP and SLCHOST_FRC_NEG_SAMP fields are five bits wide. The bits correspond to the CMD line and four DATA lines (0-3). Setting a bit causes the corresponding line to be sampled for input at the rising clock edge or falling clock edge. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 167 • SLC0HOST_SLC0_RX_UDF_INT Slave sending buffer underflow interrupt. • SLC0HOST_SLC0_TOHOST_BITn_INT (n: 0 ~ 7) Slave interrupts Host. 8.3.7.2 Slave Interrupt • SLC0INT_SLC0_RX_DSCR_ERR_INT Slave sending descriptor error. • SLC0INT_SLC0_TX_DSCR_ERR_INT Slave receiving descriptor error. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 168 Host and Slave communication register3 0x3FF55078 SLCHOST_CONF_W4_REG Host and Slave communication register4 0x3FF5507C SLCHOST_CONF_W6_REG Host and Slave communication register6 0x3FF55088 SLCHOST_CONF_W8_REG Host and Slave communication register8 0x3FF5509C SLCHOST_CONF_W9_REG Host and Slave communication register9 0x3FF550A0 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 169 Masked interrupt status 0x3FF55058 SLC0HOST_INT_CLR_REG Interrupt clear 0x3FF550D4 SLC0HOST_FUNC1_INT_ENA_REG Interrupt enable 0x3FF550DC SLCHOST_CONF_W7_REG Interrupt vector for Host to interrupt Slave 0x3FF5508C Name Description Address Access SDIO HINF registers HINF_CFG_DATA1_REG SDIO specification configuration 0x3FF4B004 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 170 When set to 1, hardware will not change the owner bit in the linked list. (R/W) SLCCONF0_SLC0_RX_RST Set this bit to reset the transmitting FSM. (R/W) SLCCONF0_SLC0_TX_RST Set this bit to reset the receiving FSM. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 171 SLC0INT_SLC_FRHOST_BIT2_INT_RAW The interrupt mark bit 2 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT1_INT_RAW The interrupt mark bit 1 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT0_INT_RAW The interrupt mark bit 0 for Host to interrupt Slave. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 172 SLC0INT_SLC_FRHOST_BIT2_INT_ST The interrupt status bit 2 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT1_INT_ST The interrupt status bit 1 for Host to interrupt Slave. (RO) SLC0INT_SLC_FRHOST_BIT0_INT_ST The interrupt status bit 0 for Host to interrupt Slave. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 173 SLC0INT_SLC_FRHOST_BIT2_INT_ENA The interrupt enable bit 2 for Host to interrupt Slave. (R/W) SLC0INT_SLC_FRHOST_BIT1_INT_ENA The interrupt enable bit 1 for Host to interrupt Slave. (R/W) Espressif Systems ESP32 TRM (Version 5.2) SLC0INT_SLC_FRHOST_BIT0_INT_ENA The interrupt enable bit 0 for Host to interrupt Slave. (R/W) Submit Documentation Feedback...
Page 174 SLC0INT_SLC_FRHOST_BIT6_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT6_INT interrupt. (WO) SLC0INT_SLC_FRHOST_BIT5_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT5_INT interrupt. (WO) SLC0INT_SLC_FRHOST_BIT4_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT4_INT interrupt. (WO) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 175 Sending will start from the address indicated by SLC0_RXLINK_ADDR. (R/W) SLC0RX_SLC0_RXLINK_STOP Set this bit to stop the linked list operation. (R/W) SLC0RX_SLC0_RXLINK_ADDR The lowest 20 bits in the initial address of Slave’s sending linked list. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 176 SLC0TX_SLC0_TXLINK_ADDR The lowest 20 bits in the initial address of Slave’s receiving linked list. (R/W) Register 8.8. SLCINTVEC_TOHOST_REG (0x4C) 0x000 0x000 0x000 Reset SLCINTVEC_SLC0_TOHOST_INTVEC The interrupt vector for Slave to interrupt Host. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 177 Reset SLCCONF1_SLC0_RX_STITCH_EN Please initialize to 0. Do not modify it. (R/W) SLCCONF1_SLC0_TX_STITCH_EN Please initialize to 0. Do not modify it. (R/W) SLCCONF1_SLC0_LEN_AUTO_CLR Please initialize to 0. Do not modify it. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 178 The addresses in parenthesis besides register names are the register addresses relative to the SDIO Slave base address (0x3FF5_5000) provided in Table Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 8.4 Register Summary. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 179 8 SDIO Slave Controller Register 8.14. SLC0HOST_TOKEN_RDATA (0x44) 0x000 0x000 0x000 Reset HOSTREG_SLC0_TOKEN1 The accumulated number of Slave’s receiving buffers. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 180 SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT3_INT_RAW The interrupt status SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT2_INT_RAW The interrupt status SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT1_INT_RAW The interrupt status SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT0_INT_RAW The interrupt status SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 181 SLC0HOST_SLC0_TOHOST_BIT3_INT_ST The masked interrupt status SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT2_INT_ST The masked interrupt status SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT1_INT_ST The masked interrupt status SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (RO) SLC0HOST_SLC0_TOHOST_BIT0_INT_ST The masked interrupt status SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 182 SLCHOST_CONF1 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF0 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 183 SLCHOST_CONF9 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF8 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 184 SLCHOST_CONF19 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF18 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 185 SLCHOST_CONF33 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF32 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 186 SLCHOST_CONF41 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF40 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 187 SLCHOST_CONF49 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF48 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 188 SLCHOST_CONF57 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF56 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 189 SLCHOST_CONF61 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) SLCHOST_CONF60 The information interaction register between Host and Slave. Both Host and Slave can access it. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 190 SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (WO) SLC0HOST_SLC0_TOHOST_BIT3_INT_CLR Set this clear SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (WO) SLC0HOST_SLC0_TOHOST_BIT2_INT_CLR Set this clear SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (WO) SLC0HOST_SLC0_TOHOST_BIT1_INT_CLR Set this clear SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (WO) SLC0HOST_SLC0_TOHOST_BIT0_INT_CLR Set this clear SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 191 SLC0HOST_FN1_SLC0_TOHOST_BIT4_INT interrupt. (R/W) SLC0HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA The interrupt enable SLC0HOST_FN1_SLC0_TOHOST_BIT3_INT interrupt. (R/W) SLC0HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA The interrupt enable SLC0HOST_FN1_SLC0_TOHOST_BIT2_INT interrupt. (R/W) SLC0HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA The interrupt enable SLC0HOST_FN1_SLC0_TOHOST_BIT1_INT interrupt. (R/W) SLC0HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA The interrupt enable SLC0HOST_FN1_SLC0_TOHOST_BIT0_INT interrupt. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 192 The addresses in parenthesis besides register names are the register addresses relative to the SDIO Slave base address (0x3FF4_B000) provided in Table Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 8.4 Register Summary. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 193 8 SDIO Slave Controller Register 8.36. HINF_CFG_DATA1_REG (0x4) Reset HINF_HIGHSPEED_ENABLE Please initialize to 1. Do not modify it. (R/W) HINF_SDIO_IOREADY1 Please initialize to 1. Do not modify it. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 194 The ESP32 memory card interface controller provides a hardware interface between the Advanced Peripheral Bus (APB) and an external memory device. The memory card interface allows the ESP32 to be connected to SDIO memory cards, MMC cards and devices with a CE-ATA interface. It supports two external cards (Card0 and Card1).
Page 195 • Bus Interface Unit (BIU): It provides APB interfaces for registers, data read and write operation by FIFO and DMA. • Card Interface Unit (CIU): It handles external memory card interface protocols. It also provides clock control. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 196 CIU, which consists of the following primary functional blocks: • Command path • Data path • SDIO interrupt control • Clock control • Mux/demux unit 9.4.2 Command Path The command path performs the following functions: Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 197 Depending on the value of the transfer_mode bit in the Command register, the data-transmit state machine adds data to the card’s data bus in a stream or in block(s). The data transmit state machine is shown in Figure 9-5. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 198 • Only one command at a time can be issued for data transfers. • During an open-ended card-write operation, if the card clock is stopped due to FIFO being empty, the Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 199 • BYTCNT - byte count • BLKSIZ - block size • CLKDIV - clock divider • CKLENA - clock enable • CLKSRC - clock source • TMOUT - timeout • CTYPE - card type Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 200 Each linked list consists of four words. As is shown below, Figure demonstrates the linked list’s structure, and Table 9-2, Table 9-3, Table 9-4, Table provide the descriptions of linked lists. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 201 When set, this bit indicates that the second ad- dress in the descriptor is the Next Descriptor ad- (Second Address Chained) dress. When this bit is set, BS2 (DES1[25:13]) should be all zeros. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 202 Name Description If the Second Address Chained (DES0[4]) bit is set, then this address contains the pointer to the physical 31:0 Next Descriptor Address memory where the Next Descriptor is present. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 203 Transmit Interrupt, if it has already been enabled. Also, the OWN bit is cleared by the DMAC by performing a write transaction to DES0. 9.9.3 DMAC Reception Initialization The DMAC reception occurs as follows: Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 204 Table 9-6. SD/MMC Timing Requirements Symbol Parameter Conditions Unit Clock Low Time = 80 MHz 11.5 12.5 — W (CKL) Clock High Time = 80 MHz 11.5 12.5 — W (CKH) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 205 If the setup time requirements for the input or output data signal are not met, users can specify the clock phase, as shown in the figure below. Figure 9-10. Clock Phase Selection Please find detailed information on the clock phase selection register CLK_EDGE_SEL in Section Registers. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 206 Card write protection (WP) status register 0x0054 TCBCNT_REG Transferred byte count register 0x005C TBBCNT_REG Transferred byte count register 0x0060 DEBNCE_REG Debounce filter time configuration register 0x0064 USRID_REG User ID (scratchpad) register 0x0068 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 207 SD/MMC controller registers can be accessed by the APB bus of the CPU. The addresses in this section are relative to the SD/MMC base address provided in Table Peripheral Address Mapping in Chapter 1 System and Memory. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 208 SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 209 (division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented because only one clock divider is supported. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 210 CCLK_ENABEL Clock-enable control for two SD card clocks and one MMC card clock is supported. 0: Clock disabled; 1: Clock enabled. In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_enable[0] is used. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 211 CARD_WIDTH4 One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit[1:0] correspond to card[1:0] respectively. Only NUM_CARDS*2 number of bits are imple- mented. (R/W) Register 9.7. BLKSIZ_REG (0x001C) 0x00200 Reset BLOCK_SIZE Block size. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 212 Bit 5 (RXDR): Receive FIFO data request Bit 4 (TXDR): Transmit FIFO data request Bit 3 (DTO): Data transfer over Bit 2 (CD): Command done Bit 1 (RE): Response error Bit 0 (CD): Card detect Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 213 Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 214 SEND_AUTO_STOP (R/W) 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer. Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 215 1: Response expected from card. CMD_INDEX Command index. (R/W) Register 9.12. RESP0_REG (0x0030) 0x000000000 Reset RESP0_REG Bit[31:0] of response. (RO) Register 9.13. RESP1_REG (0x0034) 0x000000000 Reset RESP1_REG Bit[63:32] of long response. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 216 Bit 5 (RXDR): Receive FIFO data request Bit 4 (TXDR): Transmit FIFO data request Bit 3 (DTO): Data transfer over Bit 2 (CD): Command done Bit 1 (RE): Response error Bit 0 (CD): Card detect Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 217 Bit 5 (RXDR): Receive FIFO data request Bit 4 (TXDR): Transmit FIFO data request Bit 3 (DTO): Data transfer over Bit 2 (CD): Command done Bit 1 (RE): Response error Bit 0 (CD): Card detect Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 218 FIFO_FULL FIFO is full status. (RO) FIFO_EMPTY FIFO is empty status. (RO) FIFO_TX_WATERMARK FIFO reached Transmit watermark level, not qualified with data transfer. (RO) FIFO_RX_WATERMARK FIFO reached Receive watermark level, not qualified with data transfer. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 219 FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 220 0x000000000 Reset TCBCNT_REG Number of bytes transferred by CIU unit to card. (RO) Register 9.23. TBBCNT_REG (0x0060) 0x000000000 Reset TBBCNT_REG Number of bytes transferred between Host/DMA memory and BIU FIFO. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 221 CARD_RESET[0] should be set to 1’b0 to reset card0, CARD_RESET[1] should be set to 1’b0 to reset card1.The number of bits implemented is restricted to NUM_CARDS. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 222 DBADDR_REG Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 223 IDSTS_RI Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit. (R/W) IDSTS_TI Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 224 Reset DSCADDR_REG Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 225 CCLKIN_EDGE_SAM_SEL It is used to select the clock phase of the input signal from phase90, phase180, or phase270. (R/W) CCLKIN_EDGE_DRV_SEL It is used to select the clock phase of the output signal from phase90, phase180, or phase270. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 226 10 Ethernet Media Access Controller (MAC) 10.1 Overview Features of Ethernet By using the external Ethernet PHY (physical layer), ESP32 can send and receive data via Ethernet MAC (Media Access Controller) according to the IEEE 802.3 standard, as Figure 10-1 shows.
Page 227 • Calculating the IPv4 header checksum, as well as the TCP, UDP, or ICMP checksum, and then inserting them into frames transmitted in store-and-forward mode. Ethernet Block Diagram Figure 10-2 shows the block diagram of the Ethernet. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 228 During the normal transmission of a frame from MTL, if the MAC receives an SOF without getting an EOF for the previous frame, it ignores the SOF and considers the new frame as a continuation of the previous one. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 229 RTC bit in the Operation Mode Register, the data pops up and its availability is notified to the DMA. After the DMA initiates the transmission to the AHB interface, the data transmission continues from the FIFO until the complete Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 230 64 bits and there are no CRC errors, the MAC transmitter will halt the transmission of any data frame. The duration of the pause is the decoded pause time value multiplied by the Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 231 Interrupt Mask Register to 1. For example, if bit3 of the interrupt register is set high, it indicates that a magic packet or Wake-on-LAN frame has been received in Power-down mode. The PMT Control and Status register must be read to clear this interrupt event. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 232 DAIF is set to 1, the result of unicast or multicast destination address filtering will be inverted. Similarly, when the SAIF bit is set to 1, the result of unicast SA filtering is reversed. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 233 Pass when results of perfect/group filtering match. Frames not passed are discarded. Fail when results of perfect/group filtering match. Frames not passed are discarded. The filtering parameters in the MAC Frame Filter Register described in Table 10-2 are as follows. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 234 The DMA and the Host driver communicate through two data structures: • Control and Status Registers (CSR) • Descriptor lists and data buffers For details please refer to Register Summary Linked List Descriptors. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 235 MII. This signal must be synchronized with the first nibble of the recovered frame (MII_RX_CLK) and remain synchronized till the last nibble of the recovered Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 236 MII_RX_CLK clock is provided by the PHY. The MII_TX_CLK is provided by the chip’s internal PLL or external crystal oscillator. For details regarding Figure 10-4, please refer to the clock-related registers in Register Sum- mary. Figure 10-4. MII Clock Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 237 APLL clock, as it would result in clock instability. In this case, please use an external PHY or external clock source to provide the reference clock. 10.6.2.2 RMII Clock The configuration of the RMII clock is as figure 10-6 shows. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 238 Figure 10-7. RMII Timing - Receiving Data Table 10-3. Timing Parameters - Receiving Data Timing Parameters Description Unit Clock cycle CY C Setup time – – Hold time – – Input delay Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 239 Ctrl[24:18] Status[16:7] [6:3] [2:0] Ctrl TDES1 Transmit Buffer Size[12:0] Reserved [31:29] TDES2 Buffer Address [31:0] TDES3 Next Descriptor Address[31:0] TDES4 Reserved TDES5 Reserved TDES6 Reserved TDES7 Reserved Figure 10-9. Transmit Descriptor Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 240 [24] Control Transmit Buffer. This bit is valid when the First Segment control bit (TDES0[28]) is set. In addition, CRC replacement is done only when Bit TDES0[27] is set to 1. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 241 • 2’b1: Replace the VLAN tag in frames with the Tag value pro- grammed in VLAN Tag Inclusion or Replacement Register. This option should be used only with the VLAN frames. [17] Reserved Reserved Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 242 EMACJABBER is not set. When set, this bit indicates that the DMA or MTL flushed the frame [13] FF: Frame Flushed because of a software Flush command given by the CPU. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 243 When set, this bit indicates that the MAC defers before transmis- DB: Deferred Bit sion because of the presence of a carrier. This bit is valid only in the half-duplex mode. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 244 Next Descriptor is present. 10.8.2 Receive Descriptors The structure of the receiver linked lists is shown in Figure 10-10. Table 10-9 to Table 10-13 provide the description of the linked lists. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 245 [14] DE: Descriptor Error DMA does not own the Next Descriptor. The frame is truncated. This field is valid only when the Last Descriptor (RDES0[8]) is set. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 246 When set, this bit indicates that the received frame has a non- DE: Dribble Bit Error integer multiple of bytes (odd nibbles). This bit is valid only in the MII Mode. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 247 4, the resulting behavior is undefined. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or the next descriptor depending on the value of RCH (Bit[14]). Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 248 When set, this bit indicates that the received packet is an IPv6 IPv6 Packet Received packet. This bit is updated only when Bit[10] (IPC) of Register (MAC Configuration Register) is set. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 249 • Read, Write Set, and Self Clear (R/WS/SC) • Read, Self Set, and Self Clear or Write Clear (R/SS/SC/WC) • Read Only and Write Trigger (RO/WT) • Read, Self Set, and Read Clear (R/SS/RC) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 250 EMACINTS_REG Interrupt status 0x3FF6A038 EMACINTMASK_REG Interrupt mask 0x3FF6A03C Upper 16 bits of the first 6-byte MAC ad- EMACADDR0HIGH_REG 0x3FF6A040 dress Lower 32 bits of the first 6-byte MAC EMACADDR0LOW_REG 0x3FF6A044 address Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 251 The addresses in parenthesis besides register names are the register addresses relative to the EMAC base address provided in Table Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 10.9 Register Summary. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 252 Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio Rx:Tx represented by each bit: (R/W) • 2’b00 — 1: 1 • 2’b01 — 2: 0 • 2’b10 — 3: 1 • 2’b11 — 4: 1 Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 253 (owned by the Host), the reception returns to the Suspended state and Bit[7] (RU) of Status Register is asserted. If the descriptor is available, the Rx DMA returns to the active state. (RO/WT) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 254 PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. (RO) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 255 • 3’b100: Suspended. Receive Descriptor Unavailable. • 3’b101: Running. Closing Receive Descriptor. • 3’b110: Reserved. • 3’b111: Running. Transferring the TX packets data from receive buffer to host memory. Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 256 RECV_WDT_TO When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. (R/SS/WC) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 257 TRANS_INT This bit indicates that the frame transmission is complete. When transmission is com- plete, Bit[31] (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. (R/SS/WC) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 258 DROP_GFRM When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 259 DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 260 DMAIN_ERIE When this bit is set with Normal Interrupt Summary Enable (Bit[16]), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 261 Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. (R/W) DMAIN_TIE When this bit is set with Normal Interrupt Summary Enable (Bit[16]), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 262 RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 263 Pointer updated by the DMA during operation. (RO) Register 10.14. DMARXCURRADDR_BUF_REG (0x0054) 0x000000000 Reset RECV_BUFF_ADDR_PTR The address of the current receive descriptor list. Cleared on Reset. Pointer updated by the DMA during operation. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 264 EMACJUMBOFRAME When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 265 IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset, this function is disabled. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 266 Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. 2’b00: 7 bytes of preamble. 2’b01: 5 bytes of preamble. 2’b10: 3 bytes of preamble. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 267 PAM When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is ’1’) are passed. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 268 (data remains unchanged) when it is accessed until this field is cleared by hardware (the MAC). Note that ESP32 MAC does not receive ACK from PHY during a read or write access to MIIREG and MII_DATA. (R/WS/SC) Espressif Systems ESP32 TRM (Version 5.2)
Page 269 MII_DATA This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 270 MAC does not transmit any Pause frames. In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 271 MAC. During backpressure, when the MAC receives a new frame, the trans- mitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. (R/WS/SC)(FCB)/(R/W)(BPA(backpressure activate)) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 272 • 2’b00: Rx FIFO Empty. • 2’b01: Rx FIFO fill-level below flow-control deactivate threshold. • 2’b10: Rx FIFO fill-level above flow-control activate threshold. • 2’b11: Rx FIFO Full. Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 273 MACRFFCS[0] represents the status of small FIFO Write controller. (RO) MACRPES When high, this bit indicates that the MAC MII receive protocol engine is actively receiv- ing data and not in IDLE state. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 274 • RWKPTR is 7: This filter 2 bit[15:0])/3(bit[31:16]) CRC16 register contains the CRC16 value calculated from the pattern and also the byte mask programmed to the wake-up filter register block. The polynomial: G(x) = x + 1. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 275 PWRDWN hen set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. This bit must only be set when MGKPKTEN, GLBLUCAST, or RWKPKTEN bit is set high. (R/WS/SC) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 276 TLPIEN When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. (R/SS/RC) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 277 Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. This bit is valid only when you select the optional PMT module during core configuration. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 278 EMACADDR0LOW_REG This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 279 EMACADDR1LOW_REG This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined, so the register needs to be configured after the initialization process. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 280 EMACADDR2LOW_REG This field contains the lower 32 bits of the third 6-byte MAC address. The content of this field is undefined, so the register needs to be configured after the initialization process. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 281 EMACADDR3LOW_REG This field contains the lower 32 bits of the fourth 6-byte MAC address. The content of this field is undefined, so the register needs to be configured after the initialization process. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 282 EMACADDR4LOW_REG This field contains the lower 32 bits of the fifth 6-byte MAC address. The content of this field is undefined, so the register needs to be configured after the initialization process. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 283 EMACADDR5LOW_REG This field contains the lower 32 bits of the sixth 6-byte MAC address. The content of this field is undefined, so the register needs to be configured after the initialization process. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 284 EMACADDR6LOW_REG This field contains the lower 32 bits of the seventh 6-byte MAC address. The content of this field is undefined, so the register needs to be configured after the initialization process. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 285 EMACADDR7LOW_REG This field contains the lower 32 bits of the eighth 6-byte MAC address. The content of this field is undefined, so the register needs to be configured after the initialization process. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 286 EMAC_CLK_OUT_H_DIV_NUM RMII CLK using internal APLL CLK, the half divider number, when using RMII PHY. (R/W) EMAC_CLK_OUT_DIV_NUM RMII CLK using internal APLL CLK, the whole divider number, when using RMII PHY. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 287 EMAC_MII_CLK_RX_EN Enable Ethernet RX CLK. (R/W) EMAC_MII_CLK_TX_EN Enable Ethernet TX CLK. (R/W) EMAC_INT_OSC_EN Using internal APLL CLK in RMII PHY mode. (R/W) EMAC_EXT_OSC_EN Using external APLL CLK in RMII PHY mode. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 288 EMAC_PHY_INTF_SEL The PHY interface selected. 0x0: PHY MII, 0x4: PHY RMII. (R/W) Register 10.48. EMAC_PD_SEL_REG (0x0810) Reset EMAC_RAM_PD_EN Ethernet RAM power-down enable signal. Bit[0]: TX SRAM; Bit[1]: RX SRAM. Setting the bit to 1 powers down the RAM. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 289 11 I2C Controller (I2C) 11.1 Overview An I2C (Inter-Integrated Circuit) bus can be used for communication with several external devices connected to the same bus as ESP32. The ESP32 has dedicated hardware to communicate with peripherals on the I2C bus. 11.2 Features The I2C controller has the following features: •...
Page 290 • SCL_FSM: A state machine that controls the SCL clock. The I2C_SCL_HIGH_PERIOD_REG and I2C_SCL_ LOW_PERIOD_REG registers are used to configure the frequency and duty cycle of the signal on the SCL line. • SDA_FSM: A state machine that controls the SDA data line. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 291 Notice: If the I2C pads are configured in open-drain mode, it will take longer for the signal lines to transition from a low level to a high level. The transition duration is determined together by the pull-up resistor and capacitor. The output frequency of SCL is relatively low in open-drain mode. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 292 This register specifies the length of data (in bytes) to be read or written. The maximum length is 255, while the minimum is 1. When the op_code is RSTART, STOP or END, this value is meaningless. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 293 Figure 11-5. I2C Master Writes to Slave with 7-bit Address In all subsequent figures that illustrate I2C transactions and behavior, both the I2C Master and Slave devices are assumed to be ESP32 I2C peripheral controllers for ease of demonstration. Figure 11-5 shows the I2C Master writing N bytes of data to an I2C Slave.
Page 294 One way many I2C Slave devices are designed is by exposing a register block containing various settings. The I2C Master can write one or more of these registers by sending the Slave a register address. The ESP32 I2C Espressif Systems ESP32 TRM (Version 5.2)
Page 295 Master will turn off the SCL clock and pull the SCL low to reserve the bus and prevent any other device from transacting on the bus. The controller will generate an I2C_END_DETECT_INT interrupt to notify the soft- ware. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 296 STOP signal is sent. Note: When there are more than three segments, the address of an END command in the cmd should not be altered into another command by the next segment. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 297 I2C_SLAVE_ADDR_10BIT_EN bit and preparing data to be sent in the slave RAM. In the Master, two bytes of RAM are used for a 10-bit address. Finally, the I2C _TRANS_START bit must be set to enable one transaction. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 298 To stop the transaction, the Master will configure the cmd, as the third segment shows, after detecting the I2C_END_DETECT_INT interrupt. After setting the I2C_TRANS_START bit, Master will send a STOP bit to stop the transaction. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 299 • I2C_ARBITRATION_LOST_INT: Triggered when the Master’s SCL is high, while the output value and input value of the SDA do not match. • I2C_END_DETECT_INT: Triggered when the Master deals with the END command. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 300 I2C command register 8 0x3FF53078 0x3FF67078 R/W I2C_COMD9_REG I2C command register 9 0x3FF5307C 0x3FF6707C R/W I2C_COMD10_REG I2C command register 10 0x3FF53080 0x3FF67080 R/W I2C_COMD11_REG I2C command register 11 0x3FF53084 0x3FF67084 R/W Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 301 I2C command register 12 0x3FF53088 0x3FF67088 R/W I2C_COMD13_REG I2C command register 13 0x3FF5308C 0x3FF6708C R/W I2C_COMD14_REG I2C command register 14 0x3FF53090 0x3FF67090 R/W I2C_COMD15_REG I2C command register 15 0x3FF53094 0x3FF67094 R/W Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 302 I2C_SAMPLE_SCL_LEVEL 1: sample SDA data on the SCL low level; 0: sample SDA data on the SCL high level. (R/W) I2C_SCL_FORCE_OUT 0: direct output; 1: open drain output. (R/W) I2C_SDA_FORCE_OUT 0: direct output; 1: open drain output. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 303 I2C_ACK_REC This register stores the value of the received ACK bit. (RO) Register 11.4. I2C_TO_REG (0x000c) Reset I2C_TIME_OUT_REG This register is used to configure the timeout for receiving a data bit in APB clock cycles. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 304 This value refreshes when I2C_RX_REC_FULL_INT or I2C_TRANS_COMPLETE_INT interrupt is generated. (RO) I2C_RXFIFO_START_ADDR This is the offset address of the last received data, as described in non- fifo_rx_thres_register. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 305 I2C_FIFO_ADDR_CFG_EN When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. (R/W) I2C_NONFIFO_EN Set this bit to enable APB nonfifo access. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 306 I2C_TRANS_COMPLETE_INT_RAW The raw interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. (RO) I2C_MASTER_TRAN_COMP_INT_RAW The interrupt status I2C_MASTER_TRAN_COMP_INT interrupt. (RO) I2C_ARBITRATION_LOST_INT_RAW The interrupt status I2C_ARBITRATION_LOST_INT interrupt. (RO) I2C_END_DETECT_INT_RAW The raw interrupt status bit for the I2C_END_DETECT_INT interrupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 307 I2C_MASTER_TRAN_COMP_INT_CLR Set this bit to clear the I2C_MASTER_TRAN_COMP_INT inter- rupt. (WO) I2C_ARBITRATION_LOST_INT_CLR Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. (WO) I2C_END_DETECT_INT_CLR Set this bit to clear the I2C_END_DETECT_INT interrupt. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 308 I2C_TRANS_COMPLETE_INT_ENA The interrupt enable bit for the I2C_TRANS_COMPLETE_INT terrupt. (R/W) I2C_MASTER_TRAN_COMP_INT_ENA The interrupt enable I2C_MASTER_TRAN_COMP_INT interrupt. (R/W) I2C_ARBITRATION_LOST_INT_ENA The interrupt enable bit for the I2C_ARBITRATION_LOST_INT terrupt. (R/W) I2C_END_DETECT_INT_ENA The interrupt enable bit for the I2C_END_DETECT_INT interrupt. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 309 (RO) Register 11.12. I2C_SDA_HOLD_REG (0x0030) Reset I2C_SDA_HOLD_TIME This register is used to configure the time to hold the data after the negative edge of SCL, in APB clock cycles. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 310 Reset I2C_SCL_START_HOLD_TIME This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in APB clock cycles. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 311 Register 11.18. I2C_SCL_STOP_SETUP_REG (0x004C) Reset I2C_SCL_STOP_SETUP_TIME This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in APB clock cycles. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 312 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure more information. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 313 12-1 is the system block diagram of the ESP32 I2S module. In the figure above, the value of ”n” can be either 0 or 1. There are two independent I2S modules embedded in ESP32, namely I2S0 and I2S1. Each I2S module contains a Tx (transmit) unit and a Rx (receive) unit.
Page 314 I2S mode • Configurable high-precision output clock • Full-duplex and half-duplex data transmit and receive modes • Supports multiple digital audio standards • Embedded A-law compression/decompression module • Configurable clock signal Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 315 I2Sn_CLK and BCK. For further details, please refer to the chapter entitled Reset Clock. • When ESP32 I2S works in slave mode, the master must use I2Sn_CLK as the master clock and f >= 8 Figure 12-2. I2S Clock...
Page 316 _RATE_CONF_REG. 12.4 I2S Mode The ESP32 I2S module integrates an A-law compression/decompression module to enable compression/decompression of the received audio data. The RX_PCM_BYPASS bit and the TX_PCM_BYPASS bit of register I2S_CONF1_REG should be cleared when using the A-law compression/decompression module.
Page 317 FIFO first and then read from FIFO. There are two approaches to accessing the FIFO; one is to directly access the FIFO using a CPU, the other is to access the FIFO using a DMA controller. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 318 FIFO, has not reached the set threshold and software can continue feeding data into FIFO. 12.4.4 Sending Data The ESP32 I2S module carries out a data-transmit operation in three stages: • Read data from internal storage and transfer it to FIFO • Read data to be sent from FIFO •...
Page 319 I2S_SAMPLE_RATE_CONF_REG. 12.4.5 Receiving Data The data-receive phase of the ESP32 I2S module consists of another three stages: • The input serial-bit stream is transformed into a 64-bit parallel-data stream in I2S mode. In LCD mode, the input parallel-data stream will be extended to a 64-bit parallel-data stream.
Page 320 At the third stage, CPU or DMA will read data from FIFO and write them into the internal memory directly. The register configuration that each mode corresponds to is shown in Table 12-5. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 321 12.4.6 I2S Master/Slave Mode The ESP32 I2S module can be configured to act as a master or slave device on the I2S bus. The module sup- ports slave transmitter and receiver configurations in addition to master transmitter and receiver configurations.
Page 322 CONF_REG should be set to 1 to use the PDM sending module. The I2S_TX_PDM_SIGMADELTA_IN_SHIFT bit, I2S_TX_PDM_SINC_IN_SHIFT bit, I2S_TX_PDM_LP_IN_SHIFT bit and I2S_TX_PDM_HP_IN_SHIFT bit of register I2S_PDM_CONF_REG are used to adjust the size of the input signal of each filter module. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 323 I2S_RX_PDM_SINC_DSR_16_EN PCM freq (KHz) ×128 ×64 12.5 Camera-LCD Controller There are three operational modes in the LCD mode of ESP32 I2S: • LCD master transmitting mode • Camera slave receiving mode • ADC/DAC mode Espressif Systems ESP32 TRM (Version 5.2)
Page 324 12.5.2 Camera Slave Receiving Mode ESP32 I2S supports a camera slave mode for high-speed data transfer from external camera modules. As shown in Figure 12-16, in this mode, I2S is set to slave receiving mode. Besides the 16-channel data signal bus Espressif Systems ESP32 TRM (Version 5.2)
Page 325 I2S_CONF_CHAN_REG and the I2S_RX_FIFO_MOD[2:0] bit of register I2S_FIFO_CONF_REG are set to 1. 12.5.3 ADC/DAC mode In LCD mode, ESP32’s ADC and DAC can receive data. When the I2S0 module connects to the on-chip ADC, the I2S0 module should be set to master receiving mode. Figure 12-17 shows the signal connection between the I2S0 module and the ADC.
Page 326 DAC registers. 12.6 I2S Interrupts 12.6.1 FIFO Interrupts • I2S_TX_HUNG_INT: Triggered when transmitting data is timed out. • I2S_RX_HUNG_INT: Triggered when receiving data is timed out. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 327 0x3FF4F074 0x3FF6D074 R/W I2S_CLKM_CONF_REG Bitclock configuration 0x3FF4F0AC 0x3FF6D0AC R/W I2S_SAMPLE_RATE_CONF_REG Sample rate configuration 0x3FF4F0B0 0x3FF6D0B0 R/W I2S_PD_CONF_REG Power-down register 0x3FF4F0A4 0x3FF6D0A4 R/W I2S_STATE_REG I2S status register 0x3FF4F0BC 0x3FF6D0BC RO DMA registers Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 328 0x3FF4F0B8 0x3FF6D0B8 R/W Interrupt registers I2S_INT_RAW_REG Raw interrupt status 0x3FF4F00C 0x3FF6D00C RO I2S_INT_ST_REG Masked interrupt status 0x3FF4F010 0x3FF6D010 RO I2S_INT_ENA_REG Interrupt enable bits 0x3FF4F014 0x3FF6D014 I2S_INT_CLR_REG Interrupt clear bits 0x3FF4F018 0x3FF6D018 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 329 12.7 Register Summary. Register 12.1. I2S_FIFO_WR_REG (0x0000) I2S_FIFO_WR_REG Writes the data sent by I2S into FIFO. (WO) Register 12.2. I2S_FIFO_RD_REG (0x0004) I2S_FIFO_RD_REG Stores the data that I2S receives from FIFO. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 330 I2S_RX_FIFO_RESET Set this bit to reset the receive FIFO. (R/W) I2S_TX_FIFO_RESET Set this bit to reset the transmit FIFO. (R/W) I2S_RX_RESET Set this bit to reset the receiver. (R/W) I2S_TX_RESET Set this bit to reset the transmitter. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 331 I2S_RX_WFULL_INT_RAW The raw interrupt status bit for the I2S_RX_WFULL_INT interrupt. (RO) I2S_TX_PUT_DATA_INT_RAW The raw interrupt status bit for the I2S_TX_PUT_DATA_INT interrupt. (RO) I2S_RX_TAKE_DATA_INT_RAW The raw interrupt status bit for the I2S_RX_TAKE_DATA_INT interrupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 332 I2S_RX_WFULL_INT_ST The masked interrupt status bit for the I2S_RX_WFULL_INT interrupt. (RO) I2S_TX_PUT_DATA_INT_ST The masked interrupt status bit for the I2S_TX_PUT_DATA_INT interrupt. (RO) I2S_RX_TAKE_DATA_INT_ST The masked interrupt status bit for the I2S_RX_TAKE_DATA_INT inter- rupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 333 (R/W) I2S_RX_WFULL_INT_ENA The interrupt enable bit for the I2S_RX_WFULL_INT interrupt. (R/W) I2S_TX_PUT_DATA_INT_ENA The interrupt enable bit for the I2S_TX_PUT_DATA_INT interrupt. (R/W) I2S_RX_TAKE_DATA_INT_ENA The interrupt enable bit for the I2S_RX_TAKE_DATA_INT interrupt. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 334 (WO) I2S_RX_WFULL_INT_CLR Set this bit to clear the I2S_RX_WFULL_INT interrupt. (WO) I2S_TX_PUT_DATA_INT_CLR Set this bit to clear the I2S_TX_PUT_DATA_INT interrupt. (WO) I2S_RX_TAKE_DATA_INT_CLR Set this bit to clear the I2S_RX_TAKE_DATA_INT interrupt. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 335 I2S_RX_BCK_IN_DELAY Number of delay cycles for BCK signal into the receiver. (R/W) I2S_TX_WS_IN_DELAY Number of delay cycles for WS signal into the transmitter. (R/W) I2S_TX_BCK_IN_DELAY Number of delay cycles for BCK signal into the transmitter. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 336 I2S_RXEOF_NUM_REG The length of the data to be received. It will trigger I2S_IN_SUC_EOF_INT. (R/W) Register 12.11. I2S_CONF_SINGLE_DATA_REG (0x0028) Reset I2S_CONF_SINGLE_DATA_REG The right channel or the left channel outputs constant values stored in this register according to TX_CHAN_MOD and I2S_TX_MSB_RIGHT. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 337 I2S_INLINK_RESTART Set this bit to restart inlink descriptor. (R/W) I2S_INLINK_START Set this bit to start inlink descriptor. (R/W) I2S_INLINK_STOP Set this bit to stop inlink descriptor. (R/W) I2S_INLINK_ADDR The address of first inlink descriptor. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 338 I2S_INLINK_DSCR_REG The address of current inlink descriptor. (RO) Register 12.19. I2S_INLINK_DSCR_BF0_REG (0x004c) Reset I2S_INLINK_DSCR_BF0_REG The address of next inlink descriptor. (RO) Register 12.20. I2S_INLINK_DSCR_BF1_REG (0x0050) Reset I2S_INLINK_DSCR_BF1_REG The address of next inlink data buffer. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 339 I2S_OUTLINK_DSCR_REG The address of current outlink descriptor. (RO) Register 12.22. I2S_OUTLINK_DSCR_BF0_REG (0x0058) Reset I2S_OUTLINK_DSCR_BF0_REG The address of next outlink descriptor. (RO) Register 12.23. I2S_OUTLINK_DSCR_BF1_REG (0x005c) Reset I2S_OUTLINK_DSCR_BF1_REG The address of next outlink data buffer. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 340 I2S_OUT_RST Set this bit to reset out DMA FSM. (R/W) I2S_IN_RST Set this bit to reset in DMA FSM. (R/W) Register 12.25. I2S_LC_STATE0_REG (0x006c) 0x000000000 Reset I2S_LC_STATE0_REG Receiver DMA channel status register. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 341 >= 88000/2 . (R/W) I2S_LC_FIFO_TIMEOUT When the value of FIFO hung counter is equal to this bit value, sending data-timeout interrupt or receiving data-timeout interrupt will be triggered. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 342 (R/W) I2S_TX_PCM_CONF Compress/Decompress module configuration bit. (R/W) 0: Decompress transmitted data; 1: Compress transmitted data. Register 12.29. I2S_PD_CONF_REG (0x00a4) Reset I2S_FIFO_FORCE_PU Force FIFO power-up. (R/W) I2S_FIFO_FORCE_PD Force FIFO power-down. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 343 I2S_CLKA_ENA Set this bit to enable APLL_CLK. Default is PLL_F160M_CLK. (R/W) I2S_CLKM_DIV_A Fractional clock divider’s denominator value. (R/W) I2S_CLKM_DIV_B Fractional clock divider’s numerator value. (R/W) I2S_CLKM_DIV_NUM I2S clock divider’s integral value. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 344 I2S_TX_BITS_MOD Set the bits to configure the bit length of I2S transmitter channel. (R/W) I2S_RX_BCK_DIV_NUM Bit clock configuration bit in receiver mode. (R/W) I2S_TX_BCK_DIV_NUM Bit clock configuration bit in transmitter mode. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 345 I2S_RX_PDM_EN Set this bit to enable receiver’s PDM mode. (R/W) I2S_TX_PDM_EN Set this bit to enable transmitter’s PDM mode. (R/W) Register 12.34. I2S_PDM_FREQ_CONF_REG (0x00b8) Reset I2S_TX_PDM_FP PCM-to-PDM converter’s PDM frequency parameter. (R/W) I2S_TX_PDM_FS PCM-to-PDM converter’s PCM frequency parameter. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 346 I2S_TX_FIFO_RESET_BACK This bit is used to confirm if the Tx FIFO reset is done. 1: reset is not ready; 0: reset is ready. (RO) I2S_TX_IDLE The status bit of the transmitter. 1: the transmitter is idle; 0: the transmitter is busy. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 347 IrDA (Infrared Data Exchange), or function as an RS-485 modem. All UART controllers integrated in the ESP32 feature an identical set of registers for ease of programming and flexibility. In this documentation, these controllers are referred to as UARTn, where = 0, 1, and 2, referring to UART0, UART1, and UART2, respectively.
Page 348 When UART is in Light-sleep mode (refer to Chapter Low-Power Management), Wakeup_Ctrl will start counting pulses in rxd_in. When the number or positive edges of RxD signal is greater Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 349 UART1 may impact the functioning of UART2. Therefore, these 2 registers in UART1 should only be used when the Tx_FIFO and Rx_FIFO in UART2 do not have any data. UARTn can access FIFO via register UART_FIFO_REG. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 350 You can use this interrupt to detect whether all the data from the transmitter has been sent. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 351 Software flow control regulates data flow by inserting special characters in the flow of sent data and by detecting special characters in the flow of received data. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 352 13.3.7.2 Software Flow Control Software can force the transmitter to stop transmitting data by setting UART_FORCE_XOFF, as well as force the transmitter to continue sending data by setting UART_FORCE_XON. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 353 • UART_FRM_ERR_INT: Triggered when the receiver detects a data frame error . • UART_PARITY_ERR_INT: Triggered when the receiver detects a parity error in the data. • UART_TXFIFO_EMPTY_INT: Triggered when the amount of data in the transmit-FIFO is less than what tx_mem_cnttxfifo_cnt specifies. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 354 UART_CLKDIV_REG 0x3FF40014 0x3FF50014 0x3FF6E014 ration Software flow-control UART_FLOW_CONF_REG 0x3FF40034 0x3FF50034 0x3FF6E034 R/W configuration Software flow-control UART_SWFC_CONF_REG 0x3FF4003C 0x3FF5003C 0x3FF6E03C R/W character configura- tion Sleep-mode configu- UART_SLEEP_CONF_REG 0x3FF40038 0x3FF50038 0x3FF6E038 R/W ration Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 355 UART threshold and al- UART_MEM_CONF_REG 0x3FF40058 0x3FF50058 0x3FF6E058 R/W location configuration Receive and transmit UART_MEM_CNT_STATUS_REG 0x3FF40064 0x3FF50064 0x3FF6E064 RO memory configuration Interrupt registers UART_INT_RAW_REG Raw interrupt status 0x3FF40004 0x3FF50004 0x3FF6E004 RO Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 356 In EOF link descriptor ad- UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG 0x3FF54040 0x3FF4C040 RO dress on error Current inlink descriptor, UHCI_DMA_IN_DSCR_REG 0x3FF5404C 0x3FF4C04C RO first word Current inlink descriptor, UHCI_DMA_IN_DSCR_BF0_REG 0x3FF54050 0x3FF4C050 RO second word Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 357 Interrupt registers UHCI_INT_RAW_REG Raw interrupt status 0x3FF54004 0x3FF4C004 RO UHCI_INT_ST_REG Masked interrupt status 0x3FF54008 0x3FF4C008 RO UHCI_INT_ENA_REG Interrupt enable bits 0x3FF5400C 0x3FF4C00C R/W UHCI_INT_CLR_REG Interrupt clear bits 0x3FF54010 0x3FF4C010 WO Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 358 1 System and Memory. The absolute register addresses are listed in Section 13.4.1 UART Register Summary. 13.5.2 UHCI Registers Register 13.1. UART_FIFO_REG (0x0) Reset UART_RXFIFO_RD_BYTE UARTn accesses FIFO via this register. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 359 UART_DSR_CHG_INT_RAW The raw interrupt status bit for the UART_DSR_CHG_INT interrupt. (RO) UART_RXFIFO_OVF_INT_RAW The raw interrupt status bit for the UART_RXFIFO_OVF_INT interrupt. (RO) UART_FRM_ERR_INT_RAW The raw interrupt status bit for the UART_FRM_ERR_INT interrupt. (RO) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 360 UART_PARITY_ERR_INT_RAW The raw interrupt status bit for the UART_PARITY_ERR_INT interrupt. (RO) UART_TXFIFO_EMPTY_INT_RAW The raw interrupt status bit for the UART_TXFIFO_EMPTY_INT terrupt. (RO) UART_RXFIFO_FULL_INT_RAW The raw interrupt status bit for the UART_RXFIFO_FULL_INT inter- rupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 361 UART_BRK_DET_INT_ST The masked interrupt status bit for the UART_BRK_DET_INT interrupt. (RO) UART_CTS_CHG_INT_ST The masked interrupt status bit for the UART_CTS_CHG_INT interrupt. (RO) UART_DSR_CHG_INT_ST The masked interrupt status bit for the UART_DSR_CHG_INT interrupt. (RO) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 362 UART_PARITY_ERR_INT_ST The masked interrupt status bit for the UART_PARITY_ERR_INT interrupt. (RO) UART_TXFIFO_EMPTY_INT_ST The masked interrupt status bit for the UART_TXFIFO_EMPTY_INT terrupt. (RO) UART_RXFIFO_FULL_INT_ST The masked interrupt status bit for UART_RXFIFO_FULL_INT. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 363 UART_RXFIFO_OVF_INT_ENA The interrupt enable bit for the UART_RXFIFO_OVF_INT interrupt. (R/W) UART_FRM_ERR_INT_ENA The interrupt enable bit for the UART_FRM_ERR_INT interrupt. (R/W) UART_PARITY_ERR_INT_ENA The interrupt enable bit for the UART_PARITY_ERR_INT interrupt. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 364 13 UART Controller (UART) Register 13.4. UART_INT_ENA_REG (0xC) Continued from the previous page... UART_TXFIFO_EMPTY_INT_ENA The interrupt enable bit for the UART_TXFIFO_EMPTY_INT interrupt. (R/W) UART_RXFIFO_FULL_INT_ENA The interrupt enable bit for the UART_RXFIFO_FULL_INT interrupt. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 365 UART_TXFIFO_EMPTY_INT_CLR Set this bit to clear the UART_TXFIFO_EMPTY_INT interrupt. (WO) UART_RXFIFO_FULL_INT_CLR Set this bit to clear the UART_RXFIFO_FULL_INT interrupt. This bit can be set only when data in Rx_FIFO is less than UART_RXFIFO_FULL_THRHD. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 366 UART_GLITCH_FILT When the input pulse width is lower than this value, the pulse is ignored. This register is used in the autobauding process. (R/W) UART_AUTOBAUD_EN This is the enable bit for autobaud. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 367 RX_DAT6; 9: RX_DAT7; 10: RX_PRTY; 11: RX_STP1; 12:RX_STP2; 13: RX_DL1. (RO) UART_RXFIFO_CNT (rx_mem_cnt, rxfifo_cnt) stores the number of bytes of valid data in the receive-FIFO. rx_mem_cnt register stores the three most significant bits, rxfifo_cnt stores the eight least significant bits. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 368 UART_IRDA_DPLX Set this bit to enable the IrDA loopback mode. (R/W) UART_TXD_BRK Set this bit to enable the transmitter to send NULL, when the process of sending data is completed. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 369 UART_BIT_NUM This register is used to set the length of data; 0: 5 bits, 1: 6 bits, 2: 7 bits, 3: 8 bits. (R/W) UART_PARITY_EN Set this bit to enable the UART parity check. (R/W) UART_PARITY This register is used to configure the parity check mode; 0: even, 1: odd. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 370 (rx_flow_thrhd_h3, rxfifo_full_thrhd). (R/W) Register 13.11. UART_LOWPULSE_REG (0x28) 0x0FFFFF Reset UART_LOWPULSE_MIN_CNT This register stores the value of the minimum duration of the low-level pulse. It is used in the baud rate detection process. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 371 It is used in baud rate detection process. (RO) Register 13.13. UART_RXD_CNT_REG (0x30) 0x000 Reset UART_RXD_EDGE_CNT This register stores the count of the RxD edge change. It is used in the baud rate detection process. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 372 Register 13.15. UART_SLEEP_CONF_REG (0x38) 0x0F0 Reset UART_ACTIVE_THRESHOLD When the number of positive edges of RxD signal is larger than or equal to (UART_ACTIVE_THRESHOLD+2), the system emerges from Light-sleep mode and becomes active. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 373 UART_TX_IDLE_NUM This register is used to configure the duration between transfers. (R/W) UART_RX_IDLE_THRHD When the receiver takes more time to receive Byte data than what this reg- ister indicates, it will produce a frame-end signal. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 374 UART_PRE_IDLE_NUM This register is used to configure the idle-time duration before the first at_cmd is received by the receiver. When the duration is less than what this register indicates, it will not take the next data received as an at_cmd char. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 375 UART_CHAR_NUM This register is used to configure the number of continuous at_cmd chars re- ceived by the receiver. (R/W) UART_AT_CMD_CHAR This register is used to configure the content of an at_cmd char. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 376 1 for all UART controllers, Memory will enter the low-power mode. (R/W) Register 13.24. UART_MEM_TX_STATUS_REG (0x5c) Reset UART_MEM_TX_WR_ADDR Represents the offset address to write TX FIFO. (RO) UART_MEM_TX_RD_ADDR Represents the offset address to read TX FIFO. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 377 UART_RX_MEM_CNT Refer to the description of RXFIFO_CNT. (RO) Register 13.27. UART_POSPULSE_REG (0x68) 0x0FFFFF Reset UART_POSEDGE_MIN_CNT This register stores the count of RxD positive edges. It is used in the autobaud detection process. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 378 UHCI_UART2_CE Set this bit to use UART2 and transmit or receive data. (R/W) UHCI_UART1_CE Set this bit to use UART1 and transmit or receive data. (R/W) UHCI_UART0_CE Set this bit to use UART and transmit or receive data. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 379 UHCI_RX_HUNG_INT_RAW The raw interrupt status bit for the UHCI_RX_HUNG_INT interrupt. (RO) UHCI_TX_START_INT_RAW The raw interrupt status bit for the UHCI_TX_START_INT interrupt. (RO) UHCI_RX_START_INT_RAW The raw interrupt status bit for the UHCI_RX_START_INT interrupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 380 UHCI_IN_DONE_INT_ST The masked interrupt status bit for the UHCI_IN_DONE_INT interrupt. (RO) UHCI_TX_HUNG_INT_ST The masked interrupt status bit for the UHCI_TX_HUNG_INT interrupt. (RO) UHCI_RX_HUNG_INT_ST The masked interrupt status bit for the UHCI_RX_HUNG_INT interrupt. (RO) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 381 Register 13.31. UHCI_INT_ST_REG (0x8) Continued from the previous page... UHCI_TX_START_INT_ST The masked interrupt status bit for the UHCI_TX_START_INT interrupt. (RO) UHCI_RX_START_INT_ST The masked interrupt status bit for the UHCI_RX_START_INT interrupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 382 (R/W) UHCI_RX_HUNG_INT_ENA The interrupt enable bit for the UHCI_RX_HUNG_INT interrupt. (R/W) UHCI_TX_START_INT_ENA The interrupt enable bit for the UHCI_TX_START_INT interrupt. (R/W) UHCI_RX_START_INT_ENA The interrupt enable bit for the UHCI_RX_START_INT interrupt. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 383 (WO) UHCI_RX_HUNG_INT_CLR Set this bit to clear the UHCI_RX_HUNG_INT interrupt. (WO) UHCI_TX_START_INT_CLR Set this bit to clear the UHCI_TX_START_INT interrupt. (WO) UHCI_RX_START_INT_CLR Set this bit to clear the UHCI_RX_START_INT interrupt. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 384 UHCI_OUTFIFO_WDATA This is the data that need to be pushed into DMA FIFO. (R/W) Register 13.36. UHCI_DMA_IN_POP_REG (0x20) 0x0000 Reset UHCI_INFIFO_POP Set this bit to pop data from DMA FIFO. (R/W) UHCI_INFIFO_RDATA This register stores the data popping from DMA FIFO. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 385 UHCI_INLINK_START Set this bit to start dealing with the inlink descriptors. (R/W) UHCI_INLINK_STOP Set this bit to stop dealing with the inlink descriptors. (R/W) UHCI_INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor’s address. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 386 EOF bit in this descriptor is 1. (RO) Register 13.42. UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG (0x40) 0x000000000 Reset UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG This register stores the address of the inlink descriptor when there are some errors in this descriptor. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 387 UHCI_DMA_IN_DSCR_BF0_REG The address of the last inlink descriptor x-1. (RO) Register 13.46. UHCI_DMA_IN_DSCR_BF1_REG (0x54) Reset UHCI_DMA_IN_DSCR_BF1_REG The address of the second-to-last inlink descriptor x-2. (RO) Register 13.47. UHCI_DMA_OUT_DSCR_REG (0x58) Reset UHCI_DMA_OUT_DSCR_REG The address of the current outlink descriptor y. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 388 UHCI_TX_11_ESC_EN Set this bit to enable decoding flow control char 0x11, when DMA receives data. (R/W) UHCI_TX_DB_ESC_EN Set this bit to enable decoding 0xdb char, when DMA receives data. (R/W) UHCI_TX_C0_ESC_EN Set this bit to enable decoding 0xc0 char, when DMA receives data. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 389 (R/W) UHCI_ESC_SEQ2_CHAR0 This register stores the first char used to replace the reg_esc_seq2 in data. (R/W) UHCI_ESC_SEQ2 This register stores the flow_control char to turn off the flow_control. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 390 Figure 14-2 illustrates a PWM channel with its selected timer; in this instance a high-speed channel and associ- ated high-speed timer. Fractional divider (18 bit) Figure 14-2. LED_PWM High-speed Channel Diagram Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 391 Based on the formula above, the desired duty resolution can be calculated as follows: LEDC_CLKx LEDC_HSTIMERx_DUTY_RES = log · LEDC_CLK_DIVx sig_outn Table 14-1 lists the commonly-used frequencies and their corresponding resolutions. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 392 If this value is non-zero, with a statistical chance of LEDC_DUTY_HSCHn[3..0]/16, the actual PWM pulse will be one cycle longer. This effectively increases the resolution of the PWM generator to 25 bits, but at the Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 393 1. 14.2.4 Interrupts • LEDC_DUTY_CHNG_END_LSCHn_INT: Triggered when a fade on a low-speed channel has finished. • LEDC_DUTY_CHNG_END_HSCHn_INT: Triggered when a fade on a high-speed channel has finished. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 394 Configuration register 1 for high-speed channel 0x3FF59098 LEDC_LSCH0_CONF0_REG Configuration register 0 for low-speed channel 0x3FF590A0 LEDC_LSCH1_CONF0_REG Configuration register 0 for low-speed channel 1 0x3FF590B4 LEDC_LSCH2_CONF0_REG Configuration register 0 for low-speed channel 0x3FF590C8 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 395 Initial duty cycle for low-speed channel 4 0x3FF590F8 LEDC_LSCH5_DUTY_REG Initial duty cycle for low-speed channel 5 0x3FF5910C LEDC_LSCH6_DUTY_REG Initial duty cycle for low-speed channel 6 0x3FF59120 LEDC_LSCH7_DUTY_REG Initial duty cycle for low-speed channel 7 0x3FF59134 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 396 High-level comparator value configuration regis- 0x3FF59130 ter for low-speed channel 7 Timer registers LEDC_HSTIMER0_CONF_REG High-speed timer 0 configuration 0x3FF59140 LEDC_HSTIMER1_CONF_REG High-speed timer 1 configuration 0x3FF59148 LEDC_HSTIMER2_CONF_REG High-speed timer 2 configuration 0x3FF59150 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 397 0x3FF59174 LEDC_LSTIMER3_VALUE_REG Low-speed timer 3 current counter value 0x3FF5917C Interrupt registers LEDC_INT_RAW_REG Raw interrupt status 0x3FF59180 LEDC_INT_ST_REG Masked interrupt status 0x3FF59184 LEDC_INT_ENA_REG Interrupt enable bits 0x3FF59188 LEDC_INT_CLR_REG Interrupt clear bits 0x3FF5918C Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 398 3: select hstimer3. Register 14.2. LEDC_HSCHn_HPOINT_REG (n: 0-7) (0x04+0x14*n) 0x0000 0x000000 Reset LEDC_HPOINT_HSCHn The output value changes to high when htimerx(x=[0,3]), selected by high- speed channel n, has reached LEDC_HPOINT_HSCHn[19:0]. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 399 This register is used to increase or decrease the duty cycle every time LEDC_DUTY_CYCLE_HSCHn cycles for high-speed channel n. (R/W) LEDC_DUTY_SCALE_HSCHn This register is used to increase or decrease the step scale for high- speed channel n. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 400 There are four low-speed timers, the two bits are used to select one of them for low-speed channel n. (R/W) 0: select lstimer0; 1: select lstimer1; 2: select lstimer2; 3: select lstimer3. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 401 LEDC_LPOINT_LSCHn,the output signal changes to low. (R/W) LEDC_LPOINT_LSCHn=(LEDC_HPOINT_LSCHn[19:0]+LEDC_DUTY_LSCHn[24:4]) (1) LEDC_LPOINT_LSCHn=(LEDC_HPOINT_LSCHn[19:0]+LEDC_DUTY_LSCHn[24:4] +1) (2) See the Functional Description for more information on when (1) or (2) is chosen. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 402 This register is used to increase or decrease the step scale for low- speed channel n. (R/W) Register 14.10. LEDC_LSCHn_DUTY_R_REG (n: 0-7) (0xB0+0x14*n) 0x00 0x0000000 Reset LEDC_DUTY_LSCHn_R This register represents the current duty of the output signal for low-speed channel n. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 403 ], the maximum bit width for counter is 20. (R/W) Register 14.12. LEDC_HSTIMERx_VALUE_REG (x: 0-3) (0x144+8*x) 0x0000 Reset LEDC_HSTIMERx_CNT Software can read this register to get the current counter value of high- speed timer x. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 404 ], the max bit width for counter is 20. (R/W) Register 14.14. LEDC_LSTIMERx_VALUE_REG (x: 0-3) (0x164+8*x) 0x0000 Reset LEDC_LSTIMERx_CNT Software can read this register to get the current counter value of low-speed timer x. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 405 (RO) LEDC_DUTY_CHNG_END_HSCHn_INT_ST The masked interrupt status LEDC_DUTY_CHNG_END_HSCHn_INT interrupt. (RO) LEDC_LSTIMERx_OVF_INT_ST The masked interrupt status bit for the LEDC_LSTIMERx_OVF_INT interrupt. (RO) LEDC_HSTIMERx_OVF_INT_ST The masked interrupt status bit for the LEDC_HSTIMERx_OVF_INT interrupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 406 LEDC_DUTY_CHNG_END_LSCHn_INT interrupt. (WO) LEDC_DUTY_CHNG_END_HSCHn_INT_CLR Set this clear LEDC_DUTY_CHNG_END_HSCHn_INT interrupt. (WO) LEDC_LSTIMERx_OVF_INT_CLR Set this bit to clear the LEDC_LSTIMERx_OVF_INT interrupt. (WO) LEDC_HSTIMERx_OVF_INT_CLR Set this bit to clear the LEDC_HSTIMERx_OVF_INT interrupt. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 407 14 LED PWM Controller (LEDC) Register 14.19. LEDC_CONF_REG (0x0190) Reset LEDC_APB_CLK_SEL This bit is used to set the frequency of RTC_SLOW_CLK. (R/W) 0: 8 MHz; 1: 80 MHz. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 408 APB bus, read by the transmitters, and written by the receivers. The transmitted signal can optionally be modulated by a carrier wave. Each channel is clocked by a divided-down signal derived from either the APB bus clock or REF_TICK. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 409 1, the transmitter of channel will start reading and sending data from RAM. The transmitter will receive a 32-bit value each time it reads from RAM. Of these 32 bits, the low 16-bit Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 410 Channel 0 config register 1 0x3FF56024 RMT_CH1CONF0_REG Channel 1 config register 0 0x3FF56028 RMT_CH1CONF1_REG Channel 1 config register 1 0x3FF5602C RMT_CH2CONF0_REG Channel 2 config register 0 0x3FF56030 RMT_CH2CONF1_REG Channel 2 config register 1 0x3FF56034 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 411 The addresses in parenthesis besides register names are the register addresses relative to the RMT base ad- dress provided in Table Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 15.3 Register Summary. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 412 In receive mode, when no edge is detected on the input signal for longer than REG_IDLE_THRES_CHn channel clock cycles, the receive process is finished. (R/W) RMT_DIV_CNT_CHn This register is used to set the divider for the channel clock of channel n. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 413 Set this bit to reset the write-RAM address for channel by accessing the receiver. (R/W) RMT_RX_EN_CHn Set this bit to enable receiving data on channel n. (R/W) RMT_TX_START_CHn Set this bit to start sending data on channel n. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 414 RMT_CHn_ERR_INT_ST The masked interrupt status bit for the RMT_CHn_ERR_INT interrupt. (RO) RMT_CHn_RX_END_INT_ST The masked interrupt status bit for the RMT_CHn_RX_END_INT inter- rupt. (RO) RMT_CHn_TX_END_INT_ST The masked interrupt status bit for the RMT_CHn_TX_END_INT inter- rupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 415 (WO) RMT_CHn_ERR_INT_CLR Set this bit to clear the RMT_CHn_ERR_INT interrupt. (WO) RMT_CHn_RX_END_INT_CLR Set this bit to clear the RMT_CHn_RX_END_INT interrupt. (WO) RMT_CHn_TX_END_INT_CLR Set this bit to clear the RMT_CHn_TX_END_INT interrupt. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 416 (R/W) RMT_MEM_ACCESS_EN This bit must be 1 in order to access the RMT memory. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 417 PWM channel. The MCPWM peripheral also contains a dedicated capture submodule that is used in systems where accurate timing of external events is important. ESP32 contains two MCPWM peripherals: MCPWM0 and MCPWM1. Their control registers are located in 4-KB memory blocks starting at memory locations 0x3FF5E000 and 0x3FF6C000 respectively.
Page 418 – Selection of edge polarity and prescaling of input capture signal – The capture timer can sync with a PWM timer or external signals. – Interrupt on each of the three capture channels Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 419 – Count-Down Mode: for asymmetric PWM outputs – Count-Up-Down Mode: for symmetric PWM outputs • Configure the the reloading phase (including the value and the phase) used during software and hardware synchronization. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 420 – No synchronization output generated • Configure the method of period updating. 16.3.1.3 Operator Submodule Figure 16-4. Operator Submodule The configuration parameters of the operator submodule are shown in Table 16-1. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 421 • Bypass the fault handler submodule entirely. • Set up an option for cycle-by-cycle actions clearing. • If desired, independently-configured actions can be taken when time-base counter is counting down or up. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 422 16.3.2.1 Configurations of the PWM Timer Submodule Users can configure the following functions of the PWM timer submodule: • Control how often events occur by specifying the PWM timer frequency or period. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 423 The PWM period is the result of (the value of period register × 2 + 1). Figures 16-7 16-10 show PWM timer waveforms in different modes, including timer behavior during synchro- nization events. Figure 16-7. Count-Up Mode Waveform Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 424 16 Motor Control PWM (PWM) Figure 16-8. Count-Down Mode Waveforms Figure 16-9. Count-Up-Down Mode Waveforms, Count-Down at Synchronization Event Figure 16-10. Count-Up-Down Mode Waveforms, Count-Up at Synchronization Event Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 425 The timing event generated when the PWM timer’s value equals to zero and when the PWM timer is decreasing. Figures 16-11 16-13 show the timing waveforms of U/DTEP and U/DTEZ. Figure 16-11. UTEP and UTEZ Generation in Count-Up Mode Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 426 16 Motor Control PWM (PWM) Figure 16-12. DTEP and DTEZ Generation in Count-Down Mode Figure 16-13. DTEP and UTEZ Generation in Count-Up-Down Mode Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 427 0. Therefore, when the timer is synchronized to 0, the counting direction can only be increasing, and MCPWM_TIMERn_PHASE_DIRECTION will be 0. When the timer is synchronized to the period value, the count- ing direction can only be decreasing, and MCPWM_TIMERn_PHASE_DIRECTION will be 1. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 428 • Each signal out of the PWM signal pair includes a specific pattern of dead time. • Superimposes a carrier on the PWM signal, if configured to do so. • Handles response under fault conditions. Figure 16-14 shows the block diagram of a PWM operator. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 429 16 Motor Control PWM (PWM) Figure 16-14. Submodules Inside the PWM Operator Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 430 PWM timer value is equal to A register PWM timer counts up. UTEB PWM timer value is equal to B register UT0 event Based on fault or synchronization events UT1 event Based on fault or synchronization events Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 431 1. UTEP and UTEZ do not happen simultaneously. When the PWM timer is in count-up mode, UTEP will always happen one cycle earlier than UTEZ, as demonstrated in Figure 16-11, so their action on PWM signals will Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 432 If A matches the PWM timer value and the PWM timer is incrementing, then the PWM output is pulled up. If A matches the PWM timer value while the PWM timer is decrementing, then the PWM output is pulled low. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 433 • Period A and B refer to the values written in the corresponding registers. • PWMxA and PWMxB are the output signals of PWM Operator x. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 434 The duty modulation for PWMxB is set by A, active high and proportional to A. P eriod = (P W M _T IM ERx_P ERIOD + 1) × T P T _clk Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 435 Pulses may be generated anywhere within the PWM cycle (zero – period). PWMxA’s high time duty is proportional to (B – A). P eriod = (P W M _T IM ERx_P ERIOD + 1) × T P T _clk Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 436 The duty modulation for PWMxB is set by B, active high and proportional to B. Outputs PWMxA and PWMxB can drive independent switches. P eriod = (2 × P W M _T IM ERx_P ERIOD + 1) × T P T _clk Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 437 Dead-time = B – A; Edge placement is fully programmable by software. Use the dead-time generator module if another edge delay method is required. P eriod = (2 × P W M _T IM ERx_P ERIOD + 1) × T P T _clk Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 438 NCI software-force events. NCI events are used to force PWMxA output low. Forcing on PWMxB is disabled in this case. Figure 16-20. Example of an NCI Software-Force Event on PWMxA Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 439 CNTU software-force events. UTEZ events are selected as triggers for CNTU software-force events. CNTU is used to force the PWMxB output low. Forcing on PWMxA is disabled. Figure 16-21. Example of a CNTU Software-Force Event on PWMxB Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 440 • This submodule may also be bypassed, if the dead time is configured directly in the generator submodule. Dead Time Generator’s Shadow Registers Delay registers RED and FED are shadowed with registers PWM_DTx_RED_CFG_REG and PWM_DTx_FED_CFG_REG. For the description of shadow registers, please see section 16.3.2.3. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 441 • Mode 2-5: Classical Dead Time Polarity Settings These modes represent typical configurations of polarity and should cover the active-high/low modes in available industry power switch gate drivers. The typical waveforms are shown in Figures 16-23 to 16-26. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 442 PWMxB Output = PWMxB Input with No Delay Note: For all the modes above, the position of the binary switches S4 to S8 is set to 0. Figure 16-23. Active High Complementary (AHC) Dead Time Waveforms Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 443 16 Motor Control PWM (PWM) Figure 16-24. Active Low Complementary (ALC) Dead Time Waveforms Figure 16-25. Active High (AH) Dead Time Waveforms Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 444 To calculate the delay on falling edge (FED) and rising edge (RED), use the following formulas: F ED = P W M _DT x_F ED × T DT _clk RED = P W M _DT x_RED × T DT _clk Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 445 PWM pulses. This figure do not show the first one-shot pulse and the duty-cycle control. Related details are covered in the following two sections. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 446 • (P W M _CARRIERx_OSHT W T H + 1) is the width of the first pulse (whose value ranges from 1 to 16). • (P W M _CARRIERx_P RESCALE + 1) is the PWM carrier clock’s (PC_clk) prescaler value. The first one-shot pulse and subsequent sustaining pulses are shown in Figure 16-28. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 447 Below is the formula for calculating the duty cycle: Duty = P W M _CARRIERx_DU T Y ÷ 8 All seven settings of the duty cycle are shown in Figure 16-29. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 448 • Allocation of either one-shot or cycle-by-cycle operation for each fault signal. • Generation of interrupts for each fault input. • Support for software-force tripping. • Enabling or disabling of submodule function as required. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 449 • Three capture channels, each equipped with a 32-bit time-stamp and a capture prescaler. • Independent edge polarity (rising/falling edge) selection for any capture channel. • Input capture signal prescaling (from 1 to 256). Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 450 PWM_CAP_CHx_REG. Different interrupts can be generated for different capture channels at capture events. The edge that triggers a capture event is recorded in register PWM_CAPx_EDGE. The capture event can be also forced by software. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 451 0x3FF6C058 uration PWM_DT0_FED_CFG_REG Shadow register for falling edge delay 0x3FF5E05C 0x3FF6C05C R/W (FED) PWM_DT0_RED_CFG_REG Shadow register for rising edge delay 0x3FF5E060 0x3FF6C060 R/W (RED) PWM_CARRIER0_CFG_REG Carrier enable and configuration 0x3FF5E064 0x3FF6C064 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 452 Dead time type selection and config- 0x3FF5E0C8 0x3FF6C0C8 uration PWM_DT2_FED_CFG_REG Shadow register for FED 0x3FF5E0CC 0x3FF6C0CC R/W PWM_DT2_RED_CFG_REG Shadow register for RED 0x3FF5E0D0 0x3FF6C0D0 R/W PWM_CARRIER2_CFG_REG Carrier enable and configuration 0x3FF5E0D4 0x3FF6C0D4 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 453 The addresses in parenthesis besides register names are the register addresses relative to the MCPWM base address provided in Table Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 16.4 Register Summary. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 454 (R/W) PWM_TIMER0_PERIOD Period shadow register of PWM timer0. (R/W) PWM_TIMER0_PRESCALE Period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1). (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 455 PWM_TIMER1_SYNCO_SEL PWM timer0 sync_out selection. 0: sync_in; 1: TEZ; 2: TEP; otherwise: sync_out is always 0. (R/W) PWM_TIMER1_SYNC_SW Toggling this bit will trigger a software sync. (R/W) PWM_TIMER1_SYNCI_EN When set, timer reloading with phase on sync input event is enabled. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 456 0: immediately, 1: update at TEZ, 2: update at sync, 3: update at TEZ or sync. (R/W) PWM_TIMER1_PERIOD Period shadow register of the PWM timer1. (R/W) PWM_TIMER1_PRESCALE Period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1) (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 457 PWM_TIMER1_SYNCO_SEL PWM timer1 sync_out selection. 0: sync_in; 1: TEZ; 2: TEP; otherwise: sync_out is always 0. (R/W) PWM_TIMER1_SYNC_SW Toggling this bit will trigger a software sync. (R/W) PWM_TIMER1_SYNCI_EN When set, timer reloading with phase at a sync input event is enabled. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 458 1: update at TEZ, 2: update at sync, 3: update at TEZ or sync. (R/W) PWM_TIMER2_PERIOD Period shadow register of PWM timer2. (R/W) PWM_TIMER2_PRESCALE Period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1). (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 459 PWM_TIMER2_SYNCO_SEL PWM timer2 sync_out selection. 0: sync_in; 1: TEZ; 2: TEP; other- waise: sync_out is always 0. (R/W) PWM_TIMER2_SYNC_SW Toggling this bit will trigger a software sync. (R/W) PWM_TIMER2_SYNCI_EN When set, timer reloading with phase on sync input event is enabled. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 460 PWM_TIMER0_SYNCISEL Select sync input for PWM timer0. 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 461 When all bits are set to 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 462 When all bits are set to 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 463 1: TEP; when bit2 is set to 1: TEA; when bit3 is set to 1: TEB; when bit4 is set to 1: sync; when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer’s value equals to that of register A/B.) (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 464 PWM_GEN0_A_UTEA Action on PWM0A triggered by event TEA when the timer increases. (R/W) PWM_GEN0_A_UTEP Action on PWM0A triggered by event TEP when the timer increases. (R/W) PWM_GEN0_A_UTEZ Action on PWM0A triggered by event TEZ when the timer increases. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 465 PWM_GEN0_B_UTEA Action on PWM0B triggered by event TEA when the timer increases. (R/W) PWM_GEN0_B_UTEP Action on PWM0B triggered by event TEP when the timer increases. (R/W) PWM_GEN0_B_UTEZ Action on PWM0B triggered by event TEZ when the timer increases. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 466 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) Register 16.24. PWM_DT0_FED_CFG_REG (0x005c) Reset PWM_DT0_FED Shadow register for FED. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 467 PWM_CARRIER0_PRESCALE PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = pe- riod of PWM_clk * (PWM_CARRIER0_PRESCALE + 1). (R/W) PWM_CARRIER0_EN When set, carrier0 function is enabled. When cleared, carrier0 is bypassed. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 468 PWM_FH0_F1_CBC event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) PWM_FH0_F2_CBC event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) PWM_FH0_SW_CBC Enable register for software-forced cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 469 Reset PWM_FH0_OST_ON Set and reset by hardware. If set, a one-shot mode action is on-going. (RO) PWM_FH0_CBC_ON Set and reset by hardware. If set, a cycle-by-cycle mode action is on-going. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 470 1: disable the update. (R/W) Register 16.31. PWM_GEN1_TSTMP_A_REG (0x0078) Reset PWM_GEN1_A PWM generator 1 time stamp A’s shadow register. (R/W) Register 16.32. PWM_GEN1_TSTMP_B_REG (0x007c) Reset PWM_GEN1_B PWM generator 1 time stamp B’s shadow register. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 471 PWM_GEN1_CFG_UPMETHOD Updating method for PWM generator1’s active register of configura- tion. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync. bit3: disable the update. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 472 1: TEP; when bit2 is set to 1: TEA; when bit3 is set to 1: TEB; when bit4 is set to 1: sync; when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer’s value equals to that of register A/B). (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 473 PWM_GEN1_A_UTEA Action on PWM1A triggered by event TEA when the timer increases. (R/W) PWM_GEN1_A_UTEP Action on PWM1A triggered by event TEP when the timer increases. (R/W) PWM_GEN1_A_UTEZ Action on PWM1A triggered by event TEZ when the timer increases. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 474 PWM_GEN1_B_UTEA Action on PWM1B triggered by event TEA when the timer increases. (R/W) PWM_GEN1_B_UTEP Action on PWM1B triggered by event TEP when the timer increases. (R/W) PWM_GEN1_B_UTEZ Action on PWM1B triggered by event TEZ when the timer increases. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 475 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) Register 16.38. PWM_DT1_FED_CFG_REG (0x0094) Reset PWM_DT1_FED Shadow register for FED. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 476 PWM_CARRIER1_PRESCALE PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1). (R/W) PWM_CARRIER1_EN When set, carrier1 function is enabled. When cleared, carrier1 is bypassed. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 477 (R/W) PWM_FH1_F2_CBC Enable event_f2 to will trigger cycle-by-cycle mode action. 0: disable, 1: en- able. (R/W) PWM_FH1_SW_CBC Enable the register for software-forced cycle-by-cycle mode action. 0: dis- able, 1: enable. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 478 Reset PWM_FH1_OST_ON Set and reset by hardware. If set, a one-shot mode action is on-going. (RO) PWM_FH1_CBC_ON Set and reset by hardware. If set, a cycle-by-cycle mode action is on-going. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 479 1: disable the update. (R/W) Register 16.45. PWM_GEN2_TSTMP_A_REG (0x00b0) Reset PWM_GEN2_A PWM generator 2 time stamp A’s shadow register. (R/W) Register 16.46. PWM_GEN2_TSTMP_B_REG (0x00b4) Reset PWM_GEN2_B PWM generator 2 time stamp B’s shadow register. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 480 PWM_GEN2_CFG_UPMETHOD Updating method for PWM generator2’s active register of configu- ration. 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync. bit3: disable the update. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 481 1: TEA; when bit3 is set to 1: TEB; when bit4 is set to 1: sync; when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer value equals that of register A/B.) (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 482 PWM_GEN2_A_UTEA Action on PWM2A triggered by event TEA when the timer increases. (R/W) PWM_GEN2_A_UTEP Action on PWM2A triggered by event TEP when the timer increases. (R/W) PWM_GEN2_A_UTEZ Action on PWM2A triggered by event TEZ when the timer increases. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 483 PWM_GEN2_B_UTEA Action on PWM2B triggered by event TEA when the timer increases. (R/W) PWM_GEN2_B_UTEP Action on PWM2B triggered by event TEP when the timer increases. (R/W) PWM_GEN2_B_UTEZ Action on PWM2B triggered by event TEZ when the timer increases. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 484 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W) Register 16.52. PWM_DT2_FED_CFG_REG (0x00cc) Reset PWM_DT2_FED Shadow register for FED. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 485 PWM_CARRIER2_PRESCALE PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = pe- riod of PWM_clk * (PWM_CARRIER2_PRESCALE + 1). (R/W) PWM_CARRIER2_EN When set, carrier2 function is enabled. When cleared, carrier2 is bypassed. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 486 PWM_FH2_F1_CBC event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) PWM_FH2_F2_CBC event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) PWM_FH2_SW_CBC Enable register for software-forced cycle-by-cycle mode action. 0: disable, 1: enable. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 487 Reset PWM_FH2_OST_ON Set and reset by hardware. If set, a one-shot mode action is on-going. (RO) PWM_FH2_CBC_ON Set and reset by hardware. If set, a cycle-by-cycle mode action is on-going. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 488 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix. (R/W) PWM_CAP_SYNCI_EN When set, the capture timer sync is enabled. (R/W) PWM_CAP_TIMER_EN When set, the capture timer incrementing under APB_clk is enabled. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 489 PWM_CAP0_MODE Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge; When bit1 is set to 1: enable capture on the positive edge. (R/W) PWM_CAP0_EN When set, capture on channel 0 is enabled. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 490 PWM_CAP2_MODE Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable capture on the negative edge; when bit1 is set to 1: enable capture on the positive edge. (R/W) PWM_CAP2_EN When set, capture on channel 2 is enabled. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 491 PWM_CAP2_EDGE Edge of the last capture trigger on channel 2. 0: posedge; 1: negedge. (RO) PWM_CAP1_EDGE Edge of the last capture trigger on channel 1. 0: posedge; 1: negedge. (RO) PWM_CAP0_EDGE Edge of the last capture trigger on channel 0. 0: posedge; 1: negedge. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 492 PWM_GLOBAL_FORCE_UP A toggle (software negation of this bit’s value) will trigger a forced up- date of all active registers in the MCPWM module. (R/W) PWM_GLOBAL_UP_EN The global enable of update of all active registers in the MCPWM module. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 493 INT_TIMER2_TEP_INT_ENA The enable bit for the interrupt triggered by a PWM timer 2 TEP event. (R/W) INT_TIMER1_TEP_INT_ENA The enable bit for the interrupt triggered by a PWM timer 1 TEP event. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 494 INT_TIMER2_STOP_INT_ENA The enable bit for the interrupt triggered when the timer 2 stops. (R/W) INT_TIMER1_STOP_INT_ENA The enable bit for the interrupt triggered when the timer 1 stops. (R/W) INT_TIMER0_STOP_INT_ENA The enable bit for the interrupt triggered when the timer 0 stops. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 495 INT_TIMER2_TEP_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. (RO) INT_TIMER1_TEP_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. (RO) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 496 (RO) INT_TIMER1_STOP_INT_RAW The raw status bit for the interrupt triggered when the timer 1 stops. (RO) INT_TIMER0_STOP_INT_RAW The raw status bit for the interrupt triggered when the timer 0 stops. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 497 INT_FAULT0_CLR_INT_ST The masked status bit for the interrupt triggered when event_f0 ends. (RO) INT_FAULT2_INT_ST The masked status bit for the interrupt triggered when event_f2 starts. (RO) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 498 (RO) INT_TIMER1_STOP_INT_ST The masked status bit for the interrupt triggered when the timer 1 stops. (RO) INT_TIMER0_STOP_INT_ST The masked status bit for the interrupt triggered when the timer 0 stops. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 499 INT_FAULT0_INT_CLR Set this bit to clear interrupt triggered when event_f0 starts. (WO) INT_TIMER2_TEP_INT_CLR Set this bit to clear interrupt triggered by a PWM timer 2 TEP event. (WO) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 500 INT_TIMER2_STOP_INT_CLR Set this bit to clear interrupt triggered when the timer 2 stops. (WO) INT_TIMER1_STOP_INT_CLR Set this bit to clear interrupt triggered when the timer 1 stops. (WO) INT_TIMER0_STOP_INT_CLR Set this bit to clear interrupt triggered when the timer 0 stops. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 501 The pulse counter has eight independent units, referred to as PULSE_CNT_Un. The maximum frequency of pulses supported by ESP32’s pulse counter is 40 MHz. 17.2 Functional Description 17.2.1 Architecture Figure 17-1.
Page 502 • Maximum count value: Triggered when PULSE_CNT >= PCNT_CNT_H_LIM_Un. Additionally, this will reset the counter to 0. PCNT_CNT_H_LIM_Un should be a positive number. • Minimum count value: Triggered when PULSE_CNT <= PCNT_CNT_L_LIM_Un. Additionally, this will reset Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 503 = –5: PULSE_CNT resets to 0 when the count value decreases to –5. 17.2.5 Interrupts PCNT_CNT_THR_EVENT_Un_INT: This interrupt gets triggered when one of the five channel comparators de- tects a match. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 504 PCNT_CTRL_REG Control register for all counters 0x3FF570B0 Interrupt registers PCNT_INT_RAW_REG Raw interrupt status 0x3FF57080 PCNT_INT_ST_REG Masked interrupt status 0x3FF57084 PCNT_INT_ENA_REG Interrupt enable bits 0x3FF57088 PCNT_INT_CLR_REG Interrupt clear bits 0x3FF5708C Status registers Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 505 The addresses in parenthesis besides register names are the register addresses relative to the PCNT base address provided in Table Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 17.3 Register Summary. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 506 (R/W) 1: Increase the counter; 2: Decrease the counter; 0, 3: No effect on counter PCNT_THR_THRES1_EN_Un This is the enable bit for unit n’s thres1 comparator. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 507 0x000 0x000 Reset PCNT_CNT_L_LIM_Un This register is used to configure the thr_l_lim value for unit n. (R/W) PCNT_CNT_H_LIM_Un This register is used to configure the thr_h_lim value for unit n. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 508 This register stores the current pulse count value for unit n. (RO) Register 17.5. PCNT_INT_RAW_REG (0x0080) 0x0000000 Reset PCNT_CNT_THR_EVENT_Un_INT_RAW The interrupt status PCNT_CNT_THR_EVENT_Un_INT interrupt. (RO) Register 17.6. PCNT_INT_ST_REG (0x0084) 0x0000000 Reset PCNT_CNT_THR_EVENT_Un_INT_ST The masked interrupt status PCNT_CNT_THR_EVENT_Un_INT interrupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 509 17 Pulse Count Controller (PCNT) Register 17.7. PCNT_INT_ENA_REG (0x0088) 0x0000000 Reset PCNT_CNT_THR_EVENT_Un_INT_ENA The interrupt enable PCNT_CNT_THR_EVENT_Un_INT interrupt. (R/W) Register 17.8. PCNT_INT_CLR_REG (0x008c) 0x0000000 Reset PCNT_CNT_THR_EVENT_Un_INT_CLR Set this bit to clear the PCNT_CNT_THR_EVENT_Un_INT terrupt. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 510 This register stores the current status of the counter. 0: counting value is +0 (the counter values are represented by signed binary numbers); 1: counting value is -0; 2: counting value is negative; 3: counting value is positive. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 511 There are four general-purpose timers embedded in the ESP32. They are all 64-bit generic timers based on 16-bit prescalers and 64-bit auto-reload-capable up/downcounters. The ESP32 contains two timer modules, each containing two timers. The two timers in a block are indicated by in TIMGn_Tx; the blocks themselves are indicated by an n.
Page 512 TIMGn_T0LOAD_REG 0x3FF5F020 0x3FF60020 WO TIMGn_T0_(LOADLOLOADHI)_REG Timer 1 configuration and control registers TIMGn_T1CONFIG_REG Timer 1 configuration register 0x3FF5F024 0x3FF60024 R/W TIMGn_T1LO_REG Timer 1 current value, low 32 bits 0x3FF5F028 0x3FF60028 RO Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 513 0x3FF5F06C 0x3FF6006C RO Interrupt registers TIMGn_INT_ENA_REG Interrupt enable bits 0x3FF5F098 0x3FF60098 R/W TIMGn_INT_RAW_REG Raw interrupt status 0x3FF5F09C 0x3FF6009C RO TIMGn_INT_ST_REG Masked interrupt status 0x3FF5F0A0 0x3FF600A0 RO TIMGn_INT_CLR_REG Interrupt clear bits 0x3FF5F0A4 0x3FF600A4 WO Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 514 (RO) Register 18.3. TIMGn_TxHI_REG (x: 0-1) (0x8+0x24*x) 0x000000000 Reset TIMGn_TxHI_REG After writing to TIMGn_TxUPDATE_REG, the high 32 bits of the time-base counter of timer can be read here. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 515 TIMGn_TxLOADLO_REG Low 32 bits of the value that a reload will load onto timer time-base counter. (R/W) Register 18.8. TIMGn_TxLOADHI_REG (x: 0-1) (0x1C+0x24*x) 0x000000000 Reset TIMGn_TxLOADHI_REG High 32 bits of the value that a reload will load onto timer time-base counter. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 516 TIMGn_WDT_SYS_RESET_LENGTH System reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 µs, 7: 3.2 µs. (R/W) TIMGn_WDT_FLASHBOOT_MOD_EN When set, Flash boot protection is enabled. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 517 Register 18.14. TIMGn_WDTCONFIG4_REG (0x0058) 0x0000FFFFF Reset TIMGn_WDTCONFIG4_REG Stage 2 timeout value, in MWDT clock cycles. (R/W) Register 18.15. TIMGn_WDTCONFIG5_REG (0x005c) 0x0000FFFFF Reset TIMGn_WDTCONFIG5_REG Stage 3 timeout value, in MWDT clock cycles. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 518 TIMGn_RTC_CALI_RDY Set this bit to mark the completion of calibration. (RO) TIMGn_RTC_CALI_MAX Calibration time, in cycles of the clock to be calibrated. (R/W) TIMGn_RTC_CALI_START Set this bit to starts calibration. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 519 TIMGn_INT_WDT_INT_RAW The raw interrupt status bit for the TIMGn_INT_WDT_INT interrupt. (RO) TIMGn_INT_T1_INT_RAW The raw interrupt status bit for the TIMGn_INT_T1_INT interrupt. (RO) TIMGn_INT_T0_INT_RAW The raw interrupt status bit for the TIMGn_INT_T0_INT interrupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 520 Reset TIMGn_INT_WDT_INT_CLR Set this bit to clear the TIMGn_INT_WDT_INT interrupt. (WO) TIMGn_INT_T1_INT_CLR Set this bit to clear the TIMGn_INT_T1_INT interrupt. (WO) TIMGn_INT_T0_INT_CLR Set this bit to clear the TIMGn_INT_T0_INT interrupt. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 521 19 Watchdog Timers (WDT) 19.1 Introduction The ESP32 has three watchdog timers: one in each of the two timer modules (called Main System Watchdog Timer, or MWDT) and one in the RTC module (which is called the RTC Watchdog Timer, or RWDT). These watchdog timers are intended to recover from an unforeseen fault, causing the application program to abandon its normal sequence.
Page 522 The MWDT registers are part of the timer submodule and are described in the Timer Registers section. The RWDT registers are part of the RTC submodule and are described in the RTC Registers section. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 523 20.1 Introduction The ESP32 has a number of eFuses which store system parameters. Fundamentally, an eFuse is a single bit of non-volatile memory with the restriction that once an eFuse bit is programmed to 1, it can never be reverted to 0.
Page 524 256/192/128 decryption BLOCK2* 256/192/128 key for Secure Boot BLOCK3* 256/192/128 key for user purposes disable_app_cpu disables APP CPU disable_bt disables Bluetooth pkg_version packaging version disable_cache disables cache CK8M Frequency RC_FAST_CLK frequency Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 525 Down- load Boot mode when set to uart_download_dis 1. Valid only for ESP32 ECO 20.3.1.1 System Parameter efuse_wr_disable The system parameter efuse_wr_disable determines whether all of the system parameters are write-protected. Since efuse_wr_disable is a system parameter as well, it also determines whether itself is write-protected.
Page 526 Repeat BLOCKN [255 : 128] = BLOCKN [127 : 0] = BLOCKN [127 : 0] 20.3.1.4 BLK3_part_reserve System parameters coding_scheme, BLOCK1, BLOCK2, and BLOCK3 are controlled by the parameter BLK3_part _reserve. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 527 [7:0] [7:0] XPD_SDIO_REG [14] EFUSE_BLK0_WDATA4_REG SDIO_TIEH [15] sdio_force [16] SPI_pad_config_clk [4:0] [4:0] SPI_pad_config_q [4:0] [9:5] SPI_pad_config_d [4:0] [14:10] SPI_pad_config_cs0 [4:0] EFUSE_BLK0_WDATA5_REG [19:15] vol_level_hp_inv [1:0] [23:22] dig_vol_l6 [3:0] [27:24] flash_crypt_config [3:0] [31:28] Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 528 2. Set the corresponding register bit of the system parameter bit to be programmed to 1. 3. Write 0x5A5A into register EFUSE_CONF. 4. Write 0x2 into register EFUSE_CMD. 5. Poll register EFUSE_CMD until it is 0x0, or wait for a program-done interrupt. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 529 Table 20-5. Software can use the value of each system parameter by reading the value in the corresponding register. The bit width of system parameters BLOCK1, BLOCK2, and BLOCK3 is variable. Although 256 register bits have Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 530 [4:0] [9:5] SPI_pad_config_d [4:0] [14:10] SPI_pad_config_cs0 [4:0] EFUSE_BLK0_RDATA5_REG [19:15] vol_level_hp_inv [1:0] [23:22] dig_vol_l6 [3:0] [27:24] flash_crypt_config [3:0] [31:28] coding_scheme [1:0] [1:0] console_debug_disable abstract_done_0 abstract_done_1 JTAG_disable EFUSE_BLK0_RDATA6_REG download_dis_encrypt download_dis_decrypt download_dis_cache key_status [10] Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 531 20.3.4 The Use of System Parameters by Hardware Modules Hardware modules are directly hardwired to the ESP32 in order to use the system parameters. Software cannot change this behaviour. Hardware modules use the decoded values of system parameters BLOCK1, BLOCK2, and BLOCK3, not their encoded values.
Page 532 Writes data to word 4 in eFuse BLOCK 1 0x3FF5A0a8 EFUSE_BLK1_WDATA5_REG Writes data to word 5 in eFuse BLOCK 1 0x3FF5A0ac EFUSE_BLK1_WDATA6_REG Writes data to word 6 in eFuse BLOCK 1 0x3FF5A0b0 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 533 Raw interrupt status 0x3FF5A108 EFUSE_INT_ST_REG Masked interrupt status 0x3FF5A10C EFUSE_INT_ENA_REG Interrupt enable bits 0x3FF5A110 EFUSE_INT_CLR_REG Interrupt clear bits 0x3FF5A114 Misc registers EFUSE_DAC_CONF_REG Efuse timing configuration 0x3FF5A118 EFUSE_DEC_STATUS_REG Status of 3/4 coding scheme 0x3FF5A11C Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 534 EFUSE_BLK0_RDATA1_REG This field returns the value of the lower 32 bits of WIFI_MAC_Address. (RO) Register 20.3. EFUSE_BLK0_RDATA2_REG (0x008) Reset EFUSE_RD_WIFI_MAC_CRC_HIGH This field returns the value of the higher 24 bits of WIFI_MAC_Address. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 535 EFUSE_RD_SDIO_FORCE This field returns the value of sdio_force. (RO) EFUSE_RD_SDIO_TIEH This field returns the value of SDIO_TIEH. (RO) EFUSE_RD_XPD_SDIO This field returns the value of XPD_SDIO_REG. (RO) ESFUSE_RD_CK8M_FREQ RC_FAST_CLK frequency. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 536 EFUSE_RD_SPI_PAD_CONFIG_CS0 This field returns the value of SPI_pad_config_cs0. (RO) EFUSE_RD_SPI_PAD_CONFIG_D This field returns the value of SPI_pad_config_d. (RO) EFUSE_RD_SPI_PAD_CONFIG_Q This field returns the value of SPI_pad_config_q. (RO) EFUSE_RD_SPI_PAD_CONFIG_CLK This field returns the value of SPI_pad_config_clk. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 537 Register 20.8. EFUSE_BLK0_WDATA0_REG (0x01c) Reset EFUSE_UART_DOWNLOAD_DIS This bit programs the value of uart_download_dis. Valid only for ESP32 ECO V3. (R/W) EFUSE_FLASH_CRYPT_CNT This field programs the value of flash_crypt_cnt. (R/W) EFUSE_RD_DIS This field programs the value of efuse_rd_disable. (R/W) EFUSE_WR_DIS This field programs the value of efuse_wr_disable. (R/W) Espressif Systems ESP32 TRM (Version 5.2)
Page 538 EFUSE_CHIP_VER_PKG This is the fourth bit among the four bits to program chip packaging version. (R/W) EFUSE_CHIP_VER_DIS_BT This field is programmed to disable Bluetooth. (R/W) EFUSE_CHIP_VER_DIS_APP_CPU This field is programmed to disable APP CPU. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 539 EFUSE_SPI_PAD_CONFIG_CS0 This field programs the value of SPI_pad_config_cs0. (R/W) EFUSE_SPI_PAD_CONFIG_D This field programs the value of SPI_pad_config_d. (R/W) EFUSE_SPI_PAD_CONFIG_Q This field programs the value of SPI_pad_config_q. (R/W) EFUSE_SPI_PAD_CONFIG_CLK This field programs the value of SPI_pad_config_clk. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 540 Reset EFUSE_BLK1_RDATAn_REG This field returns the value of word in BLOCK1. (RO) Register 20.16. EFUSE_BLK2_RDATAn_REG (n: 0-7) (0x58+4*n) 0x000000000 Reset EFUSE_BLK2_RDATAn_REG This field returns the value of word in BLOCK2. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 541 EFUSE_BLK3_WDATAn_REG This field programs the value of word in of BLOCK3. (R/W) Register 20.21. EFUSE_CLK_REG (0x0f8) 0x040 0x052 Reset EFUSE_CLK_SEL1 eFuse clock configuration field. (R/W) EFUSE_CLK_SEL0 eFuse clock configuration field. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 542 (R/W) Register 20.24. EFUSE_INT_RAW_REG (0x108) Reset EFUSE_PGM_DONE_INT_RAW The raw interrupt status bit for the EFUSE_PGM_DONE_INT inter- rupt. (RO) EFUSE_READ_DONE_INT_RAW The raw interrupt status bit for the EFUSE_READ_DONE_INT inter- rupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 543 EFUSE_READ_DONE_INT_ENA The interrupt enable bit for the EFUSE_READ_DONE_INT interrupt. (R/W) Register 20.27. EFUSE_INT_CLR_REG (0x114) Reset EFUSE_PGM_DONE_INT_CLR Set this bit to clear the EFUSE_PGM_DONE_INT interrupt. (WO) EFUSE_READ_DONE_INT_CLR Set this bit to clear the EFUSE_READ_DONE_INT interrupt. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 544 EFUSE_DAC_CLK_DIV eFuse timing configuration register. (R/W) Register 20.29. EFUSE_DEC_STATUS_REG (0x11c) Reset EFUSE_DEC_WARNINGS If a bit is set in this register, it means some errors were corrected while decoding the 3/4 encoding scheme. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 545 TWAI Protocol Description). ESP32 contains a TWAI controller that can be connected to a TWAI bus via an external transceiver. The TWAI controller contains numerous advanced features, and can be utilized in a wide range of use cases such as automotive products, industrial automation controls, building automation etc.
Page 546 The TWAI protocol has of the following frame types: • Data Frames • Remote Frames • Error Frames • Overload Frames • Interframe Space Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 547 The Arbitration Field primarily consists of the Frame Identifier that is transmitted most significant bit first. Given that a Dominant bit represents a logical 0, and a Recessive bit represents a logical 1: Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 548 The Extended ID (ID.17 to ID.0) is the remaining 18-bits of the 29-bit identifier for EFF. The r1 (reserved bit 1) is always Dominant. The r0 (reserved bit 0) is always Dominant. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 549 Passive Error Flag consisting of 6 Recessive bits (un- less overridden by Dominant bits of other nodes). Active Error Flags are sent by Error Active nodes, whilst Passive Error Flags are sent by Error Passive nodes. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 550 • Transmitting an Overload Frame due to condition 2 and 3 must start one bit after the detecting the Dominant bit of the condition. • A maximum of two Overload frames may be generated in order to delay the next Data or Remote Frame. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 551 CRC calculated by the Receiver does not match the CRC sequence in the received Data or Remote Frame. Form Error A Form Error is detected when a fixed-form bit field of a message contains an illegal bit. For example, the r1 and Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 552 Flag. After detecting the 14th consecutive Dominant bit (when sending an Active Error Flag or Over- load Flag), or the 8th consecutive Dominant bit following a Passive Error Flag, a Transmitter will increase Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 553 PBS1 (Phase Buffer Segment 1) can be 1 to 16 Time Quanta long. PBS1 is meant to compensate for the physical delay times within the network. PBS1 can also be lengthened for synchronization purposes. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 554 TWAI Controller. 21.4.1 Registers Block The ESP32 CPU accesses peripherals as 32-bit aligned words. However, the majority of registers in the TWAI controller only contain useful data at the least significant byte (bits [7:0]). Therefore, in these registers, bits [31:8] are ignored on writes, and return 0 on reads.
Page 555 The interrupt register indicates what events have occurred in the TWAI controller (each event is represented by a separate bit). The status register indicates the current status of the TWAI controller. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 556 ID field. Only accepted messages will be stored in the Receive FIFO. The Acceptance Filter’s registers can be programmed to specify a single filter, or specify two separate filters (dual filter mode). Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 557 Receive FIFO can be used to receive new messages. 21.5 Functional Description 21.5.1 Modes The ESP32 TWAI controller has two working modes: Reset Mode and Operation Mode. Reset Mode and Oper- ation Mode are entered by setting the TWAI_RESET_MODE bit to 1 or 0 respectively.
Page 558 • SAM: Enables triple sampling if set to 1. This is useful for low/medium speed buses where filtering spikes on the bus line is beneficial. 21.5.3 Interrupt Management The ESP32 TWAI controller provides seven interrupts, each represented by a single bit in the TWAI_INT_RAW_REG. For a particular interrupt to be triggered (i.e., its bit in TWAI_INT_RAW_REG set to 1), the interrupt’s corresponding...
Page 559 = 0: The TEC or REC error counters have exceeded the threshold value set by TWAI_ERR_WARNING_LIMIT_REG. • If TWAI_ERR_ST = 1 and TWAI_BUS_OFF_ST = 1: The TWAI controller has entered the BUS_OFF state (due to the TEC >= 256). Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 560 TX/RX data byte 1 0x58 TX/RX data byte 4 0x58 TX/RX data byte 2 0x5c TX/RX data byte 5 0x5c TX/RX data byte 3 0x60 TX/RX data byte 6 0x60 TX/RX data byte 4 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 561 Remote Frame. TWAI Data Frames are limited to a maximum payload of 8 data bytes, thus the DLC should range anywhere from 0 to 8. • X: Don’t care, can be any value. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 562 For example, when transmitting a Data Frame with 5 data bytes, the CPU should write a value of 5 to the DLC field, and then fill in data bytes 1 to 5 in the Frame Data fields. Likewise, when receiving a Data Frame with a DLC Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 563 (i.e., Single Filter Mode), or two filters (i.e., Dual Filter Mode). How the Acceptance Filter interprets the 32-bit code and mask values is dependent on whether Single Filter Mode is enabled, and the received message (i.e., SFF or EFF). Figure 21-7. Acceptance Filter Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 564 The two filters can filter the following bits of a Data or Remote Frame: • SFF – The entire 11-bit ID – RTR bit – Data byte 1 (for filter 1 only) • EFF Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 565 TWAI controller also offers an Error Warning Limit (EWL) feature that can warn the user regarding the occurrence of severe bus errors before the TWAI controller enters the Error Passive state. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 566 The TWAI controller enters the Bus-Off state when the TEC value exceeds 255. On entering the Bus-Off state, the TWAI controller will automatically do the following: • Set REC to 0 • Set TEC to 127 • Set the TWAI_BUS_OFF_ST bit to 1 • Enter Reset Mode Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 567 Bit SEG.2 Bit SEG.1 Bit SEG.0 Description start of frame ID.28 to ID.21 ID.20 to ID.18 bit SRTR bit IDE ID.17 to ID.13 ID.12 to ID.5 ID.4 to ID.0 bit RTR Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 568 Notes: • BITNO: Bit Number (BITNO) indicates the nth bit of a TWAI message where arbitration was lost. 21.6 Register Summary Name Description Address Access Configuration Registers TWAI_MODE_REG Mode Register 0x3FF6B000 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 569 The addresses in parenthesis besides register names are the register addresses relative to the TWAI base ad- dress provided in Table Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 21.6 Register Summary. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 570 (R/W) Register 21.2. TWAI_BUS_TIMING_0_REG (0x0018) 0x00 Reset TWAI_BAUD_PRESC Baud Rate Prescaler, determines the frequency dividing ratio. (RO R/W) TWAI_SYNC_JUMP_WIDTH Synchronization Jump Width (SJW), 1 ~ 4 Tq wide. (RO R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 571 TWAI_ERR_WARNING_LIMIT Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). (RO R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 572 Register 21.6. TWAI_DATA_1_REG (0x0044) Reset TWAI_TX_BYTE_1 Stored the 1st byte information of the data to be transmitted under operating mode. (WO) TWAI_ACCEPTANCE_CODE_1 Stored the 1st byte of the filter code under reset mode. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 573 Register 21.8. TWAI_DATA_3_REG (0x004C) Reset TWAI_TX_BYTE_3 Stored the 3rd byte information of the data to be transmitted under operating mode. (WO) TWAI_ACCEPTANCE_CODE_3 Stored the 3rd byte of the filter code under reset mode. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 574 Register 21.10. TWAI_DATA_5_REG (0x0054) Reset TWAI_TX_BYTE_5 Stored the 5th byte information of the data to be transmitted under operating mode. (WO) TWAI_ACCEPTANCE_MASK_1 Stored the 1st byte of the filter code under reset mode. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 575 Register 21.12. TWAI_DATA_7_REG (0x005C) Reset TWAI_TX_BYTE_7 Stored the 7th byte information of the data to be transmitted under operating mode. (WO) TWAI_ACCEPTANCE_MASK_3 Stored the 3rd byte of the filter code under reset mode. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 576 TWAI_TX_BYTE_9 Stored the 9th byte information of the data to be transmitted under operating mode. (WO) Register 21.15. TWAI_DATA_10_REG (0x0068) Reset TWAI_TX_BYTE_10 Stored the 10th byte information of the data to be transmitted under operating mode. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 577 TWAI_CLOCK_OFF This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin (RO R/W) TWAI_EXT_MODE This bit can be configured under reset mode. 1: Extended mode, compatiable with CAN2.0B; 0: Basic mode (RO R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 578 TWAI_ERR_ST 1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG. (RO) TWAI_BUS_OFF_ST 1: In bus-off status, the TWAI Controller is no longer involved in bus activities. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 579 TWAI_ECC_TYPE This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error (RO) Register 21.23. TWAI_RX_ERR_CNT_REG (0x0038) Reset TWAI_RX_ERR_CNT The RX error counter register, reflects value changes under reception status. R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 580 TWAI_TX_ERR_CNT The TX error counter register, reflects value changes under transmission status. R/W) Register 21.25. TWAI_RX_MESSAGE_CNT_REG (0x0074) Reset TWAI_RX_MESSAGE_COUNTER This register reflects the number of messages available within the RX FIFO. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 581 TWAI_ARB_LOST_INT_ST Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated. (RO) TWAI_BUS_ERR_INT_ST Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 582 TWAI_ERR_PASSIVE_INT_ENA Set this bit to 1 to enable error passive interrupt. (R/W) TWAI_ARB_LOST_INT_ENA Set this bit to 1 to enable arbitration lost interrupt. (R/W) TWAI_BUS_ERR_INT_ENA Set this bit to 1 to enable error interrupt. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 583 To enable AES-128/192/256 decryption, initialize the AES_TEXT_m_REG registers with ciphertext be- fore decryption. When decryption is finished, the AES Accelerator will store back the resulting plaintext in the AES_TEXT_m_REG registers. 22.3.3 Endianness Key Endianness Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 584 AES_TEXT_2_REG[31:24] AES_TEXT_3_REG[31:24] AES_TEXT_0_REG[23:16] AES_TEXT_1_REG[23:16] AES_TEXT_2_REG[23:16] AES_TEXT_3_REG[23:16] AES_TEXT_0_REG[15:8] AES_TEXT_1_REG[15:8] AES_TEXT_2_REG[15:8] AES_TEXT_3_REG[15:8] AES_TEXT_0_REG[7:0] AES_TEXT_1_REG[7:0] AES_TEXT_2_REG[7:0] AES_TEXT_3_REG[7:0] State AES_TEXT_0_REG[7:0] AES_TEXT_1_REG[7:0] AES_TEXT_2_REG[7:0] AES_TEXT_3_REG[7:0] AES_TEXT_0_REG[15:8] AES_TEXT_1_REG[15:8] AES_TEXT_2_REG[15:8] AES_TEXT_3_REG[15:8] AES_TEXT_0_REG[23:16] AES_TEXT_1_REG[23:16] AES_TEXT_2_REG[23:16] AES_TEXT_3_REG[23:16] AES_TEXT_0_REG[31:24] AES_TEXT_1_REG[31:24] AES_TEXT_2_REG[31:24] AES_TEXT_3_REG[31:24] Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 585 Table 22-3. AES-128 Key Endianness AES_ENDIAN_REG[1] AES_ENDIAN_REG[0] w[0] w[1] w[2] w[3] [31:24] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] [23:16] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] [15:8] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] [7:0] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] [31:24] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] [23:16] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] [15:8] AES_KEY_3_REG[23:16]...
Page 586 0x3FF01030 AES_TEXT_1_REG AES encrypted/decrypted data register 1 0x3FF01034 AES_TEXT_2_REG AES encrypted/decrypted data register 2 0x3FF01038 AES_TEXT_3_REG AES encrypted/decrypted data register 3 0x3FF0103C Control/status registers AES_START_REG AES operation start control register 0x3FF01000 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 587 Reset AES_MODE Selects the AES accelerator mode of operation. See Table 22-1 for details. (R/W) Register 22.4. AES_KEY_n_REG (n: 0-7) (0x10+4*n) 0x000000000 Reset AES_KEY_n_REG (n: 0-7) AES key material register. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 588 Register 22.5. AES_TEXT_m_REG (m: 0-3) (0x30+4*m) 0x000000000 Reset AES_TEXT_m_REG (m: 0-3) Plaintext and ciphertext register. (R/W) Register 22.6. AES_ENDIAN_REG (0x040) 0x0000000 Reset AES_ENDIAN Endianness selection register. See Table 22-2 for details. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 589 SHA_TEXT_1_REG, etc. 23.3.3 Hash Operation There is a set of control registers for SHA-1, SHA-256, SHA-384 and SHA-512, respectively; different hashing algorithms use different control registers. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 590 SHA encrypted/decrypted data register 8 0x3FF03020 SHA_TEXT_9_REG SHA encrypted/decrypted data register 9 0x3FF03024 SHA_TEXT_10_REG SHA encrypted/decrypted data register 10 0x3FF03028 SHA_TEXT_11_REG SHA encrypted/decrypted data register 11 0x3FF0302C SHA_TEXT_12_REG SHA encrypted/decrypted data register 12 0x3FF03030 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 591 Control register to initiate SHA512 operation 0x3FF030B0 WO SHA_SHA512_CONTINUE_REG Control register to continue SHA512 operation 0x3FF030B4 Control register to calculate the final SHA512 SHA_SHA512_LOAD_REG 0x3FF030B8 hash SHA_SHA512_BUSY_REG Status register for SHA512 operation 0x3FF030BC RO Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 592 SHA_SHA1_CONTINUE Write 1 to continue the SHA-1 operation with subsequent blocks. (WO) Register 23.4. SHA_SHA1_LOAD_REG (0x088) 0x00000000 Reset SHA_SHA1_LOAD Write 1 to finish the SHA-1 operation to calculate the final message hash. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 593 SHA_SHA256_START Write 1 to start an SHA-256 operation on the first message block. (WO) Register 23.7. SHA_SHA256_CONTINUE_REG (0x094) 0x00000000 Reset SHA_SHA256_CONTINUE Write 1 to continue the SHA-256 operation with subsequent blocks. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 594 SHA_SHA256_BUSY SHA-256 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. (RO) Register 23.10. SHA_SHA384_START_REG (0x0A0) 0x00000000 Reset SHA_SHA384_START Write 1 to start an SHA-384 operation on the first message block. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 595 SHA_SHA384_LOAD Write 1 to finish the SHA-384 operation to calculate the final message hash. (WO) Register 23.13. SHA_SHA384_BUSY_REG (0x0AC) 0x00000000 Reset SHA_SHA384_BUSY SHA-384 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 596 SHA_SHA512_CONTINUE Write 1 to continue the SHA-512 operation with subsequent blocks. (WO) Register 23.16. SHA_SHA512_LOAD_REG (0x0B8) 0x00000000 Reset SHA_SHA512_LOAD Write 1 to finish the SHA-512 operation to calculate the final message hash. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 597 23 SHA Accelerator (SHA) Register 23.17. SHA_SHA512_BUSY_REG (0x0BC) 0x00000000 Reset SHA_SHA512_BUSY SHA-512 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 598 In this notation, each number is represented by a sequence of base-b digits, where each base-b digit is a 32-bit word. Representing an N -bit number requires n base-b digits (all of the possible N lengths are multiples of Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 599 RSA_M_PRIME_REG will not have changed. However, X in RSA_X_MEM and r in RSA_Z_MEM will have been overwritten. In order to perform another operation, refresh the registers and memory blocks, as required. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 600 The length ˆ N of the result Z is 2 × N bits. Operands X and Y need to be extended to form arguments ˆ X and ˆ Y which have the same length ( ˆ N bits) as Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 601 Modular exponentiation mode 0x3FF02804 RSA_MODEXP_START_REG Start bit 0x3FF02808 Modular multiplication registers RSA_MULT_MODE_REG Modular multiplication mode 0x3FF0280C RSA_MULT_START_REG Start bit 0x3FF02810 Misc registers RSA_INTERRUPT_REG RSA interrupt register 0x3FF02814 RSA_CLEAN_REG RSA clean register 0x3FF02818 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 602 RSA_M_PRIME_REG This register contains M’. (R/W) Register 24.2. RSA_MODEXP_MODE_REG (0x804) Reset RSA_MODEXP_MODE This register contains the mode of modular exponentiation. (R/W) Register 24.3. RSA_MODEXP_START_REG (0x808) Reset RSA_MODEXP_START Write 1 to start modular exponentiation. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 603 RSA_INTERRUPT RSA interrupt status register. Will read 1 once an operation has completed. (R/W) Register 24.7. RSA_CLEAN_REG (0x818) Reset RSA_CLEAN This bit will read 1 once the memory initialization is completed. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 604 25 Random Number Generator (RNG) 25 Random Number Generator (RNG) 25.1 Introduction The ESP32 contains a true random number generator, which generates 32-bit random numbers that can be used for cryptographical operations, among other things. 25.2 Feature The random number generator generates true random numbers, which means random number generated from a physical process, rather than by means of an algorithm.
Page 605 Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 25.5 Register Summary. Register 25.1. RNG_DATA_REG (0x144) 0x000000000 Reset RNG_DATA_REG Random number source. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 606 26 External Memory Encryption and Decryption (FLASH) 26.1 Overview Many variants of the ESP32 must store programs and data in external flash memory. The external flash memory chip is likely to contain proprietary firmware and sensitive user data, such as credentials for gaining access to a private network.
Page 607 Steps 1 to 5, Step 6 will not use the encrypted result. Instead, the function parameter will be used. Flash Encryption Operating Conditions: Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 608 Flash encryption buffer register 2 0x3FF5B008 FLASH_ENCRYPTION_BUFFER_3_REG Flash encryption buffer register 3 0x3FF5B00C WO FLASH_ENCRYPTION_BUFFER_4_REG Flash encryption buffer register 4 0x3FF5B010 FLASH_ENCRYPTION_BUFFER_5_REG Flash encryption buffer register 5 0x3FF5B014 FLASH_ENCRYPTION_BUFFER_6_REG Flash encryption buffer register 6 0x3FF5B018 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 609 FLASH_START Set this bit to start encryption operation on data buffer. (WO) Register 26.3. FLASH_ENCRYPTION_ADDRESS_REG (0x024) 0x000000000 Reset FLASH_ENCRYPTION_ADDRESS_REG The physical address on the off-chip flash must be 8-word boundary aligned. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 610 26 External Memory Encryption and Decryption (FLASH) Register 26.4. FLASH_ENCRYPTION_DONE_REG (0x028) Reset FLASH_DONE Set this bit when encryption operation is complete. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 611 27.3.1 PID Controller In the ESP32, a PID controller acts as an indicator that signals the MMU/MPU the owner PID of the code that is currently running. The intention is that the OS updates the PID in the PID controller every time it switches context to another application.
Page 612 PID to read or write from the memory; clearing the bit disallows access. Access for PID 0 and 1 to RTC SLOW memory cannot be configured and is always enabled. Table 27-2 27-3 define the bit-to-PID mappings of the registers. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 613 1 into physical Page 2. This causes the memory access to be redirected to the same offset as the virtual memory access, yet in Page 2, which results in the effective access of physical memory address 0x3FFC_4345. The page size in this example is 8 KB. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 614 1); similarily, an SRAM2 MMU page covers + 1) 0x3F F C0000 + (pagesize ∗ n) to 0x3F F C0000 + (pagesize ∗ + 1) 1). Tables 27-5 27-6 show the resulting addresses in full. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 615 3FFC5800 3FFC5FFF 3FFD8000 3FFD9FFF 3FFCC000 3FFCCFFF 3FFC6000 3FFC67FF 3FFDA000 3FFDBFFF 3FFCD000 3FFCDFFF 3FFC6800 3FFC6FFF 3FFDC000 3FFDDFFF 3FFCE000 3FFCEFFF 3FFC7000 3FFC77FF 3FFDE000 3FFDFFFF 3FFCF000 3FFCFFFF 3FFC7800 3FFC7FFF Rest 3FFD0000 3FFDFFFF 3FFC8000 3FFDFFFF Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 616 With access to DMA, a malicious process may also be able to copy data from or to a region it cannot normally access. In order to be secure against that scenario, there is a DMA MPU which can be used to disallow DMA Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 617 0x3FFD_C000 0x3FFD_DFFF DPORT_AHB_MPU_TABLE_0_REG 8 KB 0x3FFD_E000 0x3FFD_FFFF DPORT_AHB_MPU_TABLE_0_REG Internal SRAM 1 8 KB 0x3FFE_0000 0x3FFE_1FFF DPORT_AHB_MPU_TABLE_0_REG 8 KB 0x3FFE_2000 0x3FFE_3FFF DPORT_AHB_MPU_TABLE_0_REG 8 KB 0x3FFE_4000 0x3FFE_5FFF DPORT_AHB_MPU_TABLE_0_REG 8 KB 0x3FFE_6000 0x3FFE_7FFF DPORT_AHB_MPU_TABLE_0_REG Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 618 The MMU controls five regions of virtual address space, detailed in Table 27-9. V Addr are used for accessing external flash, whereas V Addr is used for accessing external RAM. Note V Addr that V Addr is a subset of V Addr Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 619 V Addr 3104 3120 3136 3152 3168 3184 V Addr As these tables show, virtual address V Addr can only be used by processes with a PID of 0 or 1. There Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 620 • Address 0x07_2375 resides in the 7’th 64 KB-sized page. • MMU entry 0x30 needs to be set to 7 and marked as valid by setting the 8’th bit to 0. Thus, 0x007 is written to MMU entry 0x30. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 621 8 MB of memory to be mapped; 4 MB into PRO_CPU address space and a possibly different 4 MB into the APP_CPU address space, as can be seen in Table 27-15. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 622 8 is cleared when the entry is valid and set when it is not. Table 27-18 details the first MMU entry number for for all PIDs. V Addr V Addr Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 623 • Address 0x20_0876 resides in the 0x40’th 32 KB-sized page. • For the PRO_CPU, MMU entry 1152 needs to be set to 0x20 and marked as valid by clearing the 8’th bit. Thus, 0x020 is written to MMU entry 1152. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 624 DPORT_AHBLITE_MPU_TABLE_SLC_REG LED PWM Access DPORT_AHBLITE_MPU_TABLE_LEDC_REG Efuse Controller Access DPORT_AHBLITE_MPU_TABLE_EFUSE_REG Flash Encryption Access DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG PWM0 Access DPORT_AHBLITE_MPU_TABLE_PWM0_REG TIMG0 Access DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG TIMG1 Access DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG SPI2 Access DPORT_AHBLITE_MPU_TABLE_SPI2_REG SPI3 Access DPORT_AHBLITE_MPU_TABLE_SPI3_REG SYSCON Access DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 625 2 3 4 5 6 7 DPORT_AHBLITE_MPU_TABLE_X_REG bit 0 1 2 3 4 5 All the DPORT_AHBLITE_MPU_TABLE_X_REG registers are in peripheral DPort Register. Only processes with PID 0/1 can modify these registers. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 626 28 Process ID Controller (PID) 28.1 Overview The ESP32 is a dual core device and is capable of running and managing multiple processes. The PID Controller supports switching of PID when a process switch occurs. In addition to PID management, the PID Controller also facilitates management of nested interrupts by recording execution status just before an interrupt service routine is executed.
Page 627 The lowest three bits represent the process running on the CPU before the interrupt indicated by the register occurred. For details please refer to Table 28-3. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 628 If the system is currently in a nested interrupt and needs to revert to the previous interrupt, register PIDC- TRL_LEVEL_REG must be restored based on the information recorded in register PIDCTRL_FROM_n_REG Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 629 CPU NMI Interrupt Mask signal at once. Instead, PID Controller performs each task after a different num- ber of clock cycles. The numbers of clock cycles are the values specified in register PIDCTRL_PID_DELAY_REG PIDCTRL_NMI_DELAY_REG respectively. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 630 28 Process ID Controller (PID) In step 7, other tasks can be implemented as well. To do this, the cost of those tasks should be included when configuring registers PIDCTRL_PID_DELAY_REG PIDCTRL_NMI_DELAY_REG in step 3. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 631 0x3FF1F040 PIDCTRL_FROM_7_REG System status before NMI 0x3FF1F044 PIDCTRL_PID_NEW_REG New PID configuration register 0x3FF1F048 PIDCTRL_PID_CONFIRM_REG New PID confirmation register 0x3FF1F04C PIDCTRL_NMI_MASK_ENABLE_REG NMI mask enable register 0x3FF1F054 PIDCTRL_NMI_MASK_DISABLE_REG NMI mask disable register 0x3FF1F058 Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 632 The addresses in parenthesis besides register names are the register addresses relative to the PID Controller base address provided in Table Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 28.4 Register Summary. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 633 PIDCTRL_INTERRUPT_ADDR_2_REG Level 2 interrupt vector entry address. (R/W) Register 28.4. PIDCTRL_INTERRUPT_ADDR_3_REG (0x00C) 0x0400001C0 Reset PIDCTRL_INTERRUPT_ADDR_3_REG Level 3 interrupt vector entry address. (R/W) Register 28.5. PIDCTRL_INTERRUPT_ADDR_4_REG (0x010) 0x040000200 Reset PIDCTRL_INTERRUPT_ADDR_4_REG Level 4 interrupt vector entry address. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 634 PIDCTRL_INTERRUPT_ADDR_7_REG NMI interrupt vector entry address. (R/W) Register 28.9. PIDCTRL_PID_DELAY_REG (0x020) Reset PIDCTRL_PID_DELAY Delay until newly assigned PID is valid. (R/W) Register 28.10. PIDCTRL_NMI_DELAY_REG (0x024) Reset PIDCTRL_NMI_DELAY Delay for disabling CPU NMI interrupt mask signal. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 635 Register 28.12. PIDCTRL_FROM_n_REG (n: 1-7) (0x28+0x4*n) Reset PIDCTRL_PREVIOUS_STATUS_n System status before any of Level 1 to Level 6, NMI interrupts oc- curs. (R/W) Register 28.13. PIDCTRL_PID_NEW_REG (0x048) Reset PIDCTRL_PID_NEW New PID. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 636 PIDCTRL_NMI_MASK_ENABLE This bit is used to enable CPU NMI interrupt mask signal. (WO) Register 28.16. PIDCTRL_NMI_MASK_DISABLE_REG (0x058) Reset PIDCTRL_NMI_MASK_DISABLE This bit is used to disable CPU NMI interrupt mask signal. (WO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 637 (SAR ADC). There are five controllers dedicated to operating ADCs. This provides flexibility when it comes to converting analog inputs in both high-performance and low-power modes, with minimum processor overhead. ESP32 is also capable of generating analog signals, using two independent DACs and a cosine waveform gen- erator.
Page 638 The user program in ULP coprocessor can trigger a scanning process by checking and writing into specific registers, in order to verify whether the touch threshold is reached. Note: ESP32 Touch Sensor has not passed the Conducted Susceptibility (CS) test for now, and thus has limited application scenarios. 29.2.3 Available GPIOs All 10 available sensing GPIOs (pads) are listed in Table 29-1.
Page 639 SET1 & SET2. If at least one of the pads in SET1 is “touched”, the wakeup interrupt will be generated by default. It is also possible to configure the wakeup interrupt to be generated only when pads from both sets are “touched”. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 640 29.3 SAR ADC 29.3.1 Introduction ESP32 integrates two 12-bit SAR ADCs. They are managed by five SAR ADC controllers, and are able to measure signals from one to 18 analog pads. The SAR ADC controllers have specialized uses. Two of them support high-performance multiple-channel scan- ning.
Page 641 • Operation during Deep-sleep (available on one controller) • Controlled by a ULP coprocessor (available on two controllers) 29.3.3 Outline of Function The SAR ADC module’s major components, and their interconnections, are shown in Figure 29-6. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 642 29 On-Chip Sensors and Analog Signal Processing Figure 29-6. SAR ADC Outline of Function Table 29-2 lists all the analog signals that may be sent to the SAR ADC module via the ADC channels. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 643 • Some of the SAR ADC2 pins are used as strapping pins (GPIO0, GPIO2, and GPIO15), thus can not be used freely. There are five ADC controllers in ESP32: RTC ADC1 CTRL, RTC ADC2 CTRL, DIG ADC1 CTRL, DIG ADC2 CTRL and PWDET CTRL. The differences between them are summarized in Table 29-3.
Page 644 SAR analog-to-digital conversion. We use “start of scan” instead, which implies that we expect to scan a sequence of channels with DIG ADC controllers. Figure 29-8 shows a diagram of DIG SAR ADC controllers. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 645 • Alternate mode: channels of SAR ADC1 and SAR ADC2 will be scanned alternately. ESP32 supports up to a 12-bit SAR ADC resolution. The 16-bit data in DMA is composed of the ADC result and some necessary information related to the scanning mode: •...
Page 646 • Can be fully controlled by the ULP coprocessor A diagram showing the DAC channel’s function is presented in Figure 29-9. For a detailed description, see the sections below. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 647 The offset may be introduced by register SENS_SAR_DAC_DCn[7:0]. The result will be saturated. • Phase shift A phase-shift of 0 / 90 / 180 / 270 degrees can be added by setting register SENS_SAR_DAC_INVn[1:0]. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 648 A DMA controller with dual DMA channels can be used to set the output of two DAC channels. By configuring SENS_SAR_DAC_DIG_FORCE, I2S_clk can be connected to DAC clk, and I2S_DATA_OUT can be connected to DAC_DATA for direct memory access. For details, please refer to chapter DMA. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 649 SAR ADC1 and ADC2 common configuration registers APB_SARADC_CTRL_REG SAR ADC common configuration 0x60002610 APB_SARADC_CTRL2_REG SAR ADC common configuration 0x60002614 APB_SARADC_FSM_REG SAR ADC FSM sample cycles configuration 0x60002618 SAR ADC1 pattern table registers Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 650 Items 8 - 11 of pattern table 0x60002634 APB_SARADC_SAR2_PATT_TAB4_REG Items 12 - 15 of pattern table 0x60002638 29.5.3 RTC I/O For details, please refer to Section Register Summary in Chapter IO_MUX and GPIO Matrix. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 651 SENS_SAR1_SAMPLE_BIT Bit width of SAR ADC1, 00: for 9-bit, 01: for 10-bit, 10: for 11-bit, 11: for 12-bit. (R/W) SENS_SAR1_SAMPLE_CYCLE Sample cycles for SAR ADC1. (R/W) SENS_SAR1_CLK_DIV Clock divider. (R/W) Register 29.2. SENS_ULP_CP_SLEEP_CYC0_REG (0x0018) Reset SENS_ULP_CP_SLEEP_CYC0_REG Sleep cycles for ULP coprocessor timer. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 652 Reset SENS_SAR_ATTEN2_REG 2-bit attenuation for each pad, 11: 1 dB, 10: 6 dB, 01: 3 dB, 00: 0 dB, [1:0] is used for ADC2_CH0, [3:2] is used for ADC2_CH1, etc (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 653 0: the touch pad is considered touched when the value of the counter is less than the threshold. (R/W) SENS_TOUCH_XPD_WAIT The waiting time (in 8 MHz cycles) between TOUCH_START and TOUCH_XPD. (R/W) SENS_TOUCH_MEAS_DELAY The measurement’s duration (in 8 MHz cycles). (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 654 SENS_TOUCH_OUT_TH3 The threshold for touch pad 3. (R/W) Register 29.10. SENS_SAR_TOUCH_THRES3_REG (0x0064) 0x00000 0x00000 Reset SENS_TOUCH_OUT_TH4 The threshold for touch pad 4. (R/W) SENS_TOUCH_OUT_TH5 The threshold for touch pad 5. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 655 SENS_TOUCH_OUT_TH9 The threshold for touch pad 9. (R/W) Register 29.13. SENS_SAR_TOUCH_OUT1_REG (0x0070) 0x00000 0x00000 Reset SENS_TOUCH_MEAS_OUT0 The counter for touch pad 0. (RO) SENS_TOUCH_MEAS_OUT1 The counter for touch pad 1. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 656 SENS_TOUCH_MEAS_OUT5 The counter for touch pad 5. (RO) Register 29.16. SENS_SAR_TOUCH_OUT4_REG (0x007c) 0x00000 0x00000 Reset SENS_TOUCH_MEAS_OUT6 The counter for touch pad 6. (RO) SENS_TOUCH_MEAS_OUT7 The counter for touch pad 7. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 657 0: TOUCH_START & TOUCH_XPD are controlled by registers. (R/W) SENS_TOUCH_MEAS_DONE Set to 1 by FSM, indicating that touch measurement is done. (RO) SENS_TOUCH_MEAS_EN 10-bit register indicating which pads are touched. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 658 RTC ADC2 CTRL (R/W) SENS_SAR2_SAMPLE_BIT Bit width of SAR ADC2, 00: for 9-bit, 01: for 10-bit, 10: for 11-bit, 11: for 12-bit. (R/W) SENS_SAR2_SAMPLE_CYCLE Sample cycles of SAR ADC2. (R/W) SENS_SAR2_CLK_DIV Clock divider. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 659 SENS_DAC_DIG_FORCE 1: DAC1 & DAC2 use DMA, 0: DAC1 & DAC2 do not use DMA. (R/W) SENS_SW_TONE_EN 1: enable CW generator, 0: disable CW generator. (R/W) SENS_SW_FSTEP Frequency step for CW generator; can be used to adjust the frequency. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 660 The addresses in parenthesis besides register names are the register addresses relative to the base address of 0x6000_2600 (by AHB bus). The absolute register addresses are listed in Section 29.5.2 Advanced Peripheral Bus. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 661 APB_SARADC_SAR2_MUX 1: SAR ADC2 is controlled by DIG ADC2 CTRL, 0: SAR ADC2 is controlled by PWDET CTRL. (R/W) APB_SARADC_START Reserved. Please initialize to 0 (R/W) APB_SARADC_START_FORCE Reserved. Please initialize to 0 (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 662 Register 29.27. APB_SARADC_SAR1_PATT_TAB1_REG (0x1C) 0x00F0F0F0F Reset APB_SARADC_SAR1_PATT_TAB1_REG Pattern tables 0 - 3 for SAR ADC1, one byte for each pat- tern table: [31:28] pattern0_channel, [27:26] pattern0_bit_width, [25:24] pattern0_attenuation, [23:20] pattern1_channel, etc. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 663 Register 29.31. APB_SARADC_SAR2_PATT_TAB1_REG (0x2C) 0x00F0F0F0F Reset APB_SARADC_SAR2_PATT_TAB1_REG Pattern tables 0 - 3 for SAR ADC2, one byte for each pat- tern table: [31:28] pattern0_channel, [27:26] pattern0_bit_width, [25:24] pattern0_attenuation, [23:20] pattern1_channel, etc. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 664 APB_SARADC_SAR2_PATT_TAB4_REG Pattern tables 12 - 15 for SAR ADC2, one byte for each pattern table: [31:28] pattern12_channel, [27:26] pattern12_bit_width, [25:24] pat- tern12_attenuation, [23:20] pattern13_channel, etc. (R/W) 29.6.3 RTC I/O For details, please refer to Section Registers in Chapter IO_MUX and GPIO Matrix. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 665 APB Bus RTC CNTL REG RTC Memory RTC IO REG Arbiter SARADC REG I2C CTRL RTC I2C REG TSENS CTRL RTC Timer Coprocessor SAR CTRL ESP32 RTC Figure 30-1. ULP Coprocessor Diagram Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 666 0x5000_0000 to 0x5000_1FFF (8 KB). The OpCode in this chapter is represented by 4’dx, where 4 stands for 4-bit width, ’d is a decimal symbol, stands for the value of OpCode (x: 0 ~ 15). Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 667 Table 30-1. ALU Operations Among Registers Note: • ADD/SUB operations can be used to set/clear the overflow flag in ALU. • All ALU operations can be used to set/clear the zero flag in ALU. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 668 Figure 30-5. Operand Description - see Figure 30-5 ALU_sel Type of ALU operation Stage_cnt Stage count register, a separate register [7:0] used to store variables, such as loop index 8-bit value Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 669 Operand Description - see Figure 30-7 Offset 10-bit signed value, offset expressed in 32-bit words Rsrc Register R[0-3], address of destination memory, expressed in 32-bit words Rdst Register R[0-3], destination Description Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 670 ALU flag. Note: All jump addresses are expressed in 32-bit words. 30.4.5 JUMPR – Jump to a Relative Offset (Conditional upon R0) Step 4’d8 3’b1 Threshold Figure 30-9. Instruction Type — JUMPR Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 671 Stage_cnt (stage count register) and the Threshold value. 30.4.7 HALT – End the Program 4’d11 Figure 30-11. Instruction Type — HALT Description The instruction ends the operation of the processor and puts it into power-down mode. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 672 The instruction will delay the ULP coprocessor from getting into sleep for a certain number of Cycles. 30.4.11 ADC – Take Measurement with ADC Sar Mux 4’d5 Rdst Figure 30-15. Instruction Type — ADC Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 673 High part of bit mask High Low part of bit mask I2C Sel Select register SENS_I2C_SLAVE_ADDRn (n: 0-7), which contains the I²C slave address. I²C communication direction: 1 - I²C write 0 - I²C read Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 674 Figure 30-18. Instruction Type — REG_WR Operand Description - see Figure 30-18 Addr Register address, expressed in 32-bit words High Register end bit number Register start bit number Data Value to write, 8 bits Description Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 675 The ULP coprocessor puts itself into sleep mode by executing the HALT instruction. This also triggers the ULP timer to start counting RTC_SLOW_CLK ticks which, by default, originate from an internal 150 kHz RC oscillator. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 676 The ULP coprocessor can use a separate I²C controller, located in the RTC domain, to communicate with external I²C slave devices. RTC_I2C has a limited feature set, compared to I2C0/I2C1 peripherals. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 677 6. Master generates a repeated START condition. 7. Master sends slave address, with r/w bit set to 1 (“read”). 8. Slave sends one byte of data. 9. Master generates NACK. 10. Master generates a STOP condition. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 678 RTC_I2C_INT_EN_REG. Note that the bit map is shifted by 1. If a specific communication event is detected and set in register RTC_I2C_INT_ST_REG, it can then be cleared using RTC_I2C_INT_CLR_REG. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 679 SCL positive edge for a stop condition RTC I²C interrupt registers - listed only for debugging RTC_I2C_INT_CLR_REG Clear status of I²C communication events 0x3FF48C24 Enable capture of I²C communication sta- RTC_I2C_INT_EN_REG 0x3FF48C28 tus events Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 680 30 ULP Coprocessor (ULP) Status of captured I²C communication RTC_I2C_INT_ST_REG 0x3FF48C2C events Note: Interrupts from RTC_I2C are not connected. The interrupt registers above are listed only for debugging purposes. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 681 SENS_ULP_CP_START_TOP Set this bit to start the ULP coprocessor; it is active only when SENS_ULP_CP_FORCE_START_TOP = 1. (R/W) SENS_ULP_CP_FORCE_START_TOP 1: ULP coprocessor is started by SENS_ULP_CP_START_TOP; 0: ULP coprocessor is started by timer. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 682 SENS_I2C_SLAVE_ADDR2 I2C slave address 2. (R/W) SENS_I2C_SLAVE_ADDR3 I2C slave address 3. (R/W) Register 30.5. SENS_SAR_SLAVE_ADDR3_REG (0x0044) 0x000 0x000 Reset SENS_I2C_SLAVE_ADDR4 I2C slave address 4. (R/W) SENS_I2C_SLAVE_ADDR5 I2C slave address 5. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 683 + 0x0C00). The RTC base address is provided in Table Peripheral Address Mapping in Chapter System and Memory. The absolute register addresses are listed in Section 30.7.2 RTC_I2C Address Space. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 684 RTC_I2C_TRANS_START Force to generate a start condition. (R/W) RTC_I2C_MS_MODE Master (1), or slave (0). (R/W) RTC_I2C_SCL_FORCE_OUT SCL is push-pull (1) or open-drain (0). (R/W) RTC_I2C_SDA_FORCE_OUT SDA is push-pull (1) or open-drain (0). (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 685 RTC_I2C_SLAVE_RW Indicates the value of the received R/W bit, when in slave mode. (R/W) RTC_I2C_ACK_VAL The value of ACK signal on the bus. (R/W) Register 30.11. RTC_I2C_TIMEOUT_REG (0x00c) Reset RTC_I2C_TIMEOUT Maximum number of RTC_FAST_CLK cycles that the transmission can take. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 686 (R/W) RTC_I2C_ARBITRATION_LOST_INT_CLR Clear interrupt upon losing control of the bus, when in master mode. (R/W) RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR Clear interrupt upon completion of transaction, when in slave mode. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 687 Register 30.15. RTC_I2C_INT_ST_REG (0x02c) Reset RTC_I2C_TIME_OUT_INT_ST Detected timeout. (R/O) RTC_I2C_TRANS_COMPLETE_INT_ST Detected stop pattern on I2C bus. (R/O) RTC_I2C_MASTER_TRAN_COMP_INT_ST Transaction completed, when in master mode. (R/O) RTC_I2C_ARBITRATION_LOST_INT_ST Bus control lost, when in master mode. (R/O) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 688 Register 30.17. RTC_I2C_SCL_HIGH_PERIOD_REG (0x038) Reset RTC_I2C_SCL_HIGH_PERIOD Number of RTC_FAST_CLK cycles when SCL == 1. (R/W) Register 30.18. RTC_I2C_SCL_START_PERIOD_REG (0x040) Reset RTC_I2C_SCL_START_PERIOD Number of RTC_FAST_CLK cycles to wait before generating a start condition. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 689 30 ULP Coprocessor (ULP) Register 30.19. RTC_I2C_SCL_STOP_PERIOD_REG (0x044) Reset RTC_I2C_SCL_STOP_PERIOD Number of RTC_FAST_CLK cycles to wait before generating a stop condition. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 690 31 Low-Power Management (RTC_CNTL) 31.1 Introduction ESP32 offers efficient and flexible power-management technology to achieve the best balance between power consumption, wakeup latency and available wakeup sources. Users can select out of five predefined power modes of the main processors to suit specific needs of the application. In addition, to save power in power- sensitive applications, control may be executed by the Ultra-Low-Power coprocessor (ULP coprocessor), while the main processors are in Deep-sleep mode.
Page 691 The low-power management unit includes voltage regulators, a power controller, power switch cells, power do- main isolation cells, etc. Figure 31-1 shows the high-level architecture of ESP32’s low-power management. 31.3.2 Digital Core Voltage Regulator The built-in voltage regulator can convert the external power supply (typically 3.3V) to 1.1V to support the internal digital core.
Page 692 4. When the regulator output is 3.3V or 1.8V, the output current comes from the pin VDD3P3_RTC. Figure 31-4 shows the structure of a flash voltage regulator. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 693 PLL, power switch and isolation cells to generate power-gating, clock-gating, and reset signals. As for the low-power management, RTC is composed of the following modules (see Figure 31-6): • RTC main state machine: records the power state. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 694 • Retention registers: always-on registers of 8 x 32 bits, serving as data storage. • RTC IO pads: 18 always-on analog pads, usually functioning as wake-up sources. Figure 31-6. RTC Structure Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 695 RTC_FAST_CLK RC_FAST_CLK RTC Memory RTC Fast Clock RTC Registers RTC Clock Figure 31-7. RTC Low-Power Clocks For the digital core, LOW_POWERE_CLK is switched among four sources. For details, please see Figure Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 696 (FPU) or force-power-down (FPD). Since the power domains can be power-gated independently, there are many combinations for different applications. Table 31-1 shows how the power domains in ESP32 are controlled. Table 31-1. RTC Power Domains RTC Main State S/W Options...
Page 697 7. Each internal SRAM can be power-gated independently. 31.3.9 Predefined Power Modes In ESP32, we recommend that you always use the predefined power modes first, before trying to tune each power control signal. The predefined power modes should cover most scenarios: •...
Page 698 – The RTC memory and fast RTC memory are powered down. – Current consumption: ∼ 4.5 µA. – Wake-up source: RTC timer only. – Wake-up latency: less than 1 ms. – Recommended for ultra-low-power infrequently-connected Wi-Fi/Bluetooth applications. Figure 31-10. Power Modes Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 699 31 Low-Power Management (RTC_CNTL) By default, ESP32-S2 first enters the Modem-sleep mode after a system reset and can be configured to Active mode when transmitting or receiving packets. After the CPU stalls for a while, the chip can enter several low- power modes.
Page 700 31.3.11 Reject Sleep ESP32 implements a hardware mechanism that equips the chip with the ability to reject to sleep, which prevents the chip from going to sleep unexpectedly when some peripherals are still working but not detected by the CPU, thus guaranteeing the proper functioning of the peripherals.
Page 701 5. When the CPU is powered up, after ROM unpacking and some necessary initialization, the CRC is calcu- lated again. If the result matches with register RTC_CNTL_RTC_STORE6_REG[31:0], the CPU will jump to the entry address. The boot flow is shown in Figure 31-11. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 702 31 Low-Power Management (RTC_CNTL) Figure 31-11. ESP32 Boot Flow 31.4 Register Summary Notes: • The registers listed below have been grouped according to their functionality. This particular grouping does not reflect the exact sequential order in which they are stored in memory.
Page 703 XTAL control by external pads 0x3FF4805C RTC_CNTL_SLP_REJECT_CONF_REG Reject cause and enable control 0x3FF48064 RTC_CNTL_CPU_PERIOD_CONF_REG CPU period select 0x3FF48068 RTC_CNTL_CLK_CONF_REG Configuration of RTC clocks 0x3FF48070 RTC_CNTL_SDIO_CONF_REG SDIO configuration 0x3FF48074 RTC_CNTL_SW_CPU_STALL_REG Stall of CPUs 0x3FF480AC Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 704 The addresses in parenthesis besides register names are the register addresses relative to the Low-power Management (RTC) base address provided in Table Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register addresses are listed in Section 31.4 Register Summary. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 705 RTC_CNTL_BBPLL_FORCE_PD BB_PLL force power down. (R/W) RTC_CNTL_BBPLL_I2C_FORCE_PU BB_PLL_I2C force power up. (R/W) RTC_CNTL_BBPLL_I2C_FORCE_PD BB_PLL _I2C force power down. (R/W) RTC_CNTL_BB_I2C_FORCE_PU BB_I2C force power up. (R/W) RTC_CNTL_BB_I2C_FORCE_PD BB_I2C force power down. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 706 Register 31.2. RTC_CNTL_SLP_TIMER0_REG (0x0004) 0x000000000 Reset RTC_CNTL_SLP_TIMER0_REG RTC sleep timer low 32 bits. (R/W) Register 31.3. RTC_CNTL_SLP_TIMER1_REG (0x0008) 0x00000 Reset RTC_CNTL_MAIN_TIMER_ALARM_EN Timer alarm enable bit. (R/W) RTC_CNTL_SLP_VAL_HI RTC sleep timer high 16 bits. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 707 RTC_CNTL_TIME_VALID Indicates that the register is updated. (RO) Register 31.5. RTC_CNTL_TIME0_REG (0x0010) 0x000000000 Reset RTC_CNTL_TIME0_REG RTC timer low 32 bits. (RO) Register 31.6. RTC_CNTL_TIME1_REG (0x0014) 0x00000 Reset RTC_CNTL_TIME_HI RTC timer high 16 bits. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 708 RTC_CNTL_SLP_WAKEUP Sleep wake-up bit. (R/W) RTC_CNTL_SDIO_ACTIVE_IND SDIO active indication. (RO) RTC_CNTL_ULP_CP_SLP_TIMER_EN ULP coprocessor timer enable bit. (R/W) RTC_CNTL_TOUCH_SLP_TIMER_EN Touch timer enable bit. (R/W) Register 31.8. RTC_CNTL_TIMER1_REG (0x001C) Reset RTC_CNTL_CPU_STALL_EN CPU stall enable bit. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 709 RTC_CNTL_MIN_TIME_CK8M_OFF Minimal amount of cycles in RTC_SLOW_CLK to power down CK8M. (R/W) RTC_CNTL_ULPCP_TOUCH_START_WAIT Awaited cycles in RTC_SLOW_CLK before ULP coprocessor/touch controller starts working. (R/W) Register 31.10. RTC_CNTL_TIMER5_REG (0x002C) 0x080 Reset RTC_CNTL_MIN_SLP_VAL Minimal amount of sleep cycles in RTC_SLOW_CLK. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 710 RTC_CNTL_PLLA_FORCE_PD PLLA force power down. (R/W) Register 31.12. RTC_CNTL_RESET_STATE_REG (0x0034) Reset RTC_CNTL_PROCPU_STAT_VECTOR_SEL PRO_CPU state vector selection. (R/W) RTC_CNTL_APPCPU_STAT_VECTOR_SEL APP_CPU state vector selection. (R/W) RTC_CNTL_RESET_CAUSE_APPCPU Reset cause for APP_CPU. (RO) RTC_CNTL_RESET_CAUSE_PROCPU Reset cause for PRO_CPU. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 711 31 Low-Power Management (RTC_CNTL) Register 31.13. RTC_CNTL_WAKEUP_STATE_REG (0x0038) 0x000 Reset RTC_CNTL_GPIO_WAKEUP_FILTER Enable filter for GPIO wake-up event. (R/W) RTC_CNTL_WAKEUP_ENA Wake-up enable bitmap. (R/W) RTC_CNTL_WAKEUP_CAUSE Wake-up cause. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 712 RTC_CNTL_SDIO_IDLE_INT_ENA The interrupt enable bit for the RTC_CNTL_SDIO_IDLE_INT inter- rupt. (R/W) RTC_CNTL_SLP_REJECT_INT_ENA The interrupt enable bit for the RTC_CNTL_SLP_REJECT_INT in- terrupt. (R/W) RTC_CNTL_SLP_WAKEUP_INT_ENA The interrupt enable bit for the RTC_CNTL_SLP_WAKEUP_INT interrupt. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 713 RTC_CNTL_SDIO_IDLE_INT_RAW The raw interrupt status bit for the RTC_CNTL_SDIO_IDLE_INT interrupt. (RO) RTC_CNTL_SLP_REJECT_INT_RAW The raw interrupt status bit for the RTC_CNTL_SLP_REJECT_INT interrupt. (RO) RTC_CNTL_SLP_WAKEUP_INT_RAW The raw interrupt status bit for the RTC_CNTL_SLP_WAKEUP_INT interrupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 714 RTC_CNTL_SDIO_IDLE_INT_ST The masked interrupt status bit for the RTC_CNTL_SDIO_IDLE_INT interrupt. (RO) RTC_CNTL_SLP_REJECT_INT_ST The masked interrupt status bit for the RTC_CNTL_SLP_REJECT_INT interrupt. (RO) RTC_CNTL_SLP_WAKEUP_INT_ST The masked interrupt status bit for the RTC_CNTL_SLP_WAKEUP_INT interrupt. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 715 RTC_CNTL_SLP_REJECT_INT_CLR Set this bit to clear the RTC_CNTL_SLP_REJECT_INT interrupt. (WO) RTC_CNTL_SLP_WAKEUP_INT_CLR Set this bit to clear the RTC_CNTL_SLP_WAKEUP_INT interrupt. (WO) Register 31.18. RTC_CNTL_STOREn_REG (n: 0-3) (0x004C+4*n) Reset RTC_CNTL_STOREn_REG 32-bit general-purpose retention register. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 716 • 1: the chip is not in sleep modes (i.e. running normally). (RO) Register 31.20. RTC_CNTL_EXT_XTL_CONF_REG (0x005C) Reset RTC_CNTL_XTL_EXT_CTR_EN Enable control XTAL with external pads. (R/W) RTC_CNTL_XTL_EXT_CTR_LV 0: power down XTAL at high level, 1: power down XTAL at low level. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 717 Register 31.22. RTC_CNTL_SLP_REJECT_CONF_REG (0x0064) Reset RTC_CNTL_REJECT_CAUSE Sleep reject cause. (RO) RTC_CNTL_DEEP_SLP_REJECT_EN Enable reject for deep sleep. (R/W) RTC_CNTL_LIGHT_SLP_REJECT_EN Enable reject for light sleep. (R/W) RTC_CNTL_SDIO_REJECT_EN Enable SDIO reject. (R/W) RTC_CNTL_GPIO_REJECT_EN Enable GPIO reject. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 718 31 Low-Power Management (RTC_CNTL) Register 31.23. RTC_CNTL_CPU_PERIOD_CONF_REG (0x0068) Reset RTC_CNTL_RTC_CPUPERIOD_SEL CPU period selection. (R/W) RTC_CNTL_CPUSEL_CONF CPU selection option. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 719 RTC_CNTL_ENB_CK8M_DIV 1: RC_FAST_DIV_CLK is actually CK8M, 0: RC_FAST_DIV_CLK is CK8M divided by 256. (R/W) RTC_CNTL_ENB_CK8M Disable CK8M and RC_FAST_DIV_CLK. (R/W) RTC_CNTL_CK8M_DIV RC_FAST_DIV_CLK divider. 00: div128, 01: div256, 10: div512, 11: div1024. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 720 RTC_CNTL_SDIO_TIEH SW option for SDIO_TIEH; active only when reg_rtc_cntl_sdio_force == 1. (R/W) RTC_CNTL_SDIO_FORCE 1: use SW option to control SDIO_VREG; 0: use state machine to control SDIO_VREG. (R/W) RTC_CNTL_SDIO_VREG_PD_EN Power down SDIO_VREG in sleep; active only when reg_rtc_cntl_sdio_force == 0. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 721 RTC_CNTL_DBIAS_SLP RTC_DBIAS during sleep. (R/W) RTC_CNTL_SCK_DCAP Used to adjust the frequency of RTC slow clock. (R/W) RTC_CNTL_DIG_VREG_DBIAS_WAK Digital voltage regulator DBIAS during wake-up. (R/W) RTC_CNTL_DIG_VREG_DBIAS_SLP Digital voltage regulator DBIAS during sleep. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 722 RTC_CNTL_FORCE_ISO rtc_peri force isolation. (R/W) RTC_CNTL_SLOWMEM_FORCE_ISO RTC memory force isolation. (R/W) RTC_CNTL_SLOWMEM_FORCE_NOISO RTC memory force no isolation. (R/W) RTC_CNTL_FASTMEM_FORCE_ISO Fast RTC memory force isolation. (R/W) RTC_CNTL_FASTMEM_FORCE_NOISO Fast RTC memory force no isolation. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 723 RTC_CNTL_INTER_RAM1_FORCE_PD Internal SRAM 1 force power down. (R/W) RTC_CNTL_INTER_RAM0_FORCE_PU Internal SRAM 0 force power up. (R/W) RTC_CNTL_INTER_RAM0_FORCE_PD Internal SRAM 0 force power down. (R/W) RTC_CNTL_ROM0_FORCE_PU ROM force power up. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 724 Continued from the previous page... RTC_CNTL_ROM0_FORCE_PD ROM force power down. (R/W) RTC_CNTL_LSLP_MEM_FORCE_PU Memories in digital core force power up in sleep mode. (R/W) RTC_CNTL_LSLP_MEM_FORCE_PD Memories in digital core force power down in sleep mode. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 725 RTC_CNTL_ROM0_FORCE_ISO ROM force isolation. (R/W) RTC_CNTL_DG_PAD_FORCE_HOLD Digital pad force hold. (R/W) RTC_CNTL_DG_PAD_FORCE_UNHOLD Digital pad force un-hold. (R/W) RTC_CNTL_DG_PAD_FORCE_ISO Digital pad force isolation. (R/W) RTC_CNTL_DG_PAD_FORCE_NOISO Digital pad force no isolation. (R/W) Continued on the next page... Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 726 4: RTC reset stage enable. (R/W) RTC_CNTL_WDT_STG0 1: interrupt stage enable, 2: CPU reset stage enable, 3: system reset stage enable, 4: RTC reset stage enable. (R/W) RTC_CNTL_WDT_EN Enable RTC WDT. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 727 RTC_CNTL_WDT_FEED SW feeds WDT. (WO) Register 31.33. RTC_CNTL_WDTWPROTECT_REG (0x00A4) 0x050D83AA1 Reset RTC_CNTL_WDTWPROTECT_REG If the register contains a different value than 0x50d83aa1, write protection for the RTC watchdog (RWDT) is enabled. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 728 == 0x86 (100001 10) will stall PRO_CPU, see also RTC_CNTL_OPTIONS0_REG. (R/W) RTC_CNTL_SW_STALL_APPCPU_C1 reg_rtc_cntl_sw_stall_appcpu_c1[5:0], reg_rtc_cntl_sw_stall_appcpu_c0[1:0] == 0x86 (100001 10) will stall APP_CPU, see also RTC_CNTL_OPTIONS0_REG. (R/W) Register 31.35. RTC_CNTL_STOREn_REG (n: 4-7) (0x00B0+4*(n-4)) Reset RTC_CNTL_STOREn_REG 32-bit general-purpose retention register. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 729 RTC_CNTL_PDAC2_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W) RTC_CNTL_PDAC1_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W) RTC_CNTL_ADC2_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W) RTC_CNTL_ADC1_HOLD_FORCE Set to preserve pad’s state during hibernation. (R/W) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 730 Register 31.37. RTC_CNTL_EXT_WAKEUP1_REG (0x00CC) Reset RTC_CNTL_EXT_WAKEUP1_STATUS_CLR Clear external wakeup1 status. (WO) RTC_CNTL_EXT_WAKEUP1_SEL Bitmap to select RTC pads for external wakeup1. (R/W) Register 31.38. RTC_CNTL_EXT_WAKEUP1_STATUS_REG (0x00D0) Reset RTC_CNTL_EXT_WAKEUP1_STATUS EXT1 wakeup source status. (RO) Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 731 Note that there may be some variation of brownout voltage level between each ESP32 chip. 0: 2.43 V ± 0.05; 1: 2.48 V ± 0.05; 2: 2.58 V ± 0.05; 3: 2.62 V ± 0.05; 4: 2.67 V ± 0.05; 5: 2.70 V ± 0.05; 6: 2.77 V ± 0.05; 7: 2.80 V ±...
Page 732 Non-maskable interrupt. Register. Read/write. Software can read and write to these bits. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 733 Glossary Read-only. Software can only read these bits. Write-only. Software can only write to these bits. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 734 Group (TIMG): Updated description TIMGn_WDT_CLK_PRESCALE • Chapter 29 On-Chip Sensors and Analog Signal Processing: Updated register APB_SARADC_FSM_REG • Chapter 31 Low-Power Management (RTC_CNTL): Updated description of RTC_CNTL_WDTWPROTECT_REG Cont’d on next page Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 735 – Added a note about limited applications of touch sensor in Section 29.2.2 Features – Removed internal signals vdd33, pa_pkdet1, pa_pkdet2 • Added description about “reject sleep” in Chapter 31 Low-Power Management (RTC_CNTL) Cont’d on next page Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 736 17 Pulse Count Controller (PCNT) • Updated Section 18.3 in Chapter 18 Timer Group (TIMG) • Added two notes in Chapter 29 On-Chip Sensors and Analog Signal Processing Cont’d on next page Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 737 21 Two-wire Automotive Interface (TWAI) Updated description in Chapter 25 Random Number Generator (RNG) Updated the description in Section 30.4.2 Fixed typos in Table and in Section Cont’d on next page Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 738 Chapter 2020.09 V4.3 25 Random Number Generator (RNG) Added information about uart_download_dis in Chapter eFuse Controller Updated the description of SPI_ADDR_REG SPI_SLV_WR_STATUS_REG Cont’d on next page Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 739 Management: • Added description of register RTC_CNTL_WDTCONFIG0_REG • Modified description of register RTC_CNTL_WDTCONFIGn_REG Changes to Chapter Coprocessor: • Updated description in sections 30.4.13 30.4.14 • Fixed typos Cont’d on next page Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 740 • Removed the description of registers RTC_I2C_SLAVE_TRAN_COMP_INT_ENA and RTC_I2C_SLAVE_TRAN_COMP_INT_ST; Changes to Chapter Low-Power Management: • Updated default value description register RTC_CNTL_DBROWN_OUT_THRES; • Updated the description of register RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA; Added documentation feedback hyperlink. Cont’d on next page Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 741 • Updated the description of register RMT_APB_CONF_REG. Updated description registers UART_RX_TOUT_THRHD, UART_RXFIFO_FULL_INT_CLR, UART_RXFIFO_FULL_INT_CLR. Updated the images in Section 4.8: ESP32 I/O Pad Power Supplies; Updated Section 11.3.3: I C Bus Timing; Added notes to Section 14.2.3: LED_PWM Channels; 2018.06 V3.4 Updated the ”Maximum count value”...
Page 742 IO_MUX and GPIO Matrix; Added Chapter Coprocessor. Added Chapter On-Chip Sensors and Analog Signal Processing; Added Section Audio PLL; 2017.05 V1.7 Updated Section eFuse Controller Register Summary; Cont’d on next page Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 743 Section I2C Controller Registers. Added Chapter PID/MPU/MMU; 2016.11 V1.2 Updated Section IO_MUX and GPIO Matrix Register Summary; Updated Section LED_PWM Register Summary. 2016.09 V1.1 Added Chapter Controller. 2016.08 V1.0 Initial release. Espressif Systems ESP32 TRM (Version 5.2) Submit Documentation Feedback...
Page 744 The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark of Bluetooth SIG. All trade names, trademarks and registered trademarks mentioned in this document are property of their respective owners, and are hereby acknowledged. Copyright © 2024 Espressif Systems (Shanghai) Co., Ltd. All rights reserved. www.espressif.com...