Espressif ESP32 Technical Reference Manual page 71

4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)
31
x x x x x x x
GPIO_STATUS_INT_W1TS GPIO0-31 interrupt status set register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_STATUS_INT will be set. (WO)
31
x x x x x x x
GPIO_STATUS_INT_W1TC GPIO0-31 interrupt status clear register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_STATUS_INT will be cleared. (WO)
31
0 0 0 0 0 0 0
GPIO_STATUS1_INT GPIO32-39 interrupt status register. Each bit can be either of the two interrupt
sources for the two CPUs. The enable bits in GPIO_PINn_INT_ENA, corresponding to the 13-16
bits in GPIO_PINn_REG
Espressif Systems
Register 4.17. GPIO_STATUS_W1TS_REG (0x0048)
x x x x x x x x
Register 4.18. GPIO_STATUS_W1TC_REG (0x004c)
x x x x x x x x
Register 4.19. GPIO_STATUS1_REG (0x0050)
0 0 0 0 0 0 0 0
should be set to 1. (R/W)
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x x x x x x x x
x x x x x x x x
0 0 0 0 0 0 0 0
71
x x x x x x x x
x x x x x x x x
8 7
0 x x x x x x x
ESP32 TRM (Version 5.2)
0
x
Reset
0
x Reset
0
x
Reset