Espressif ESP32 Technical Reference Manual page 257

10 Ethernet Media Access Controller (MAC)
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RECV_PROC_STOP This bit is asserted when the Receive Process enters the Stopped state.
(R/SS/WC)
RECV_BUF_UNAVAIL This bit indicates that the host owns the Next Descriptor in the Receive List and
the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive
descriptors, the host should change the ownership of the descriptor and issue a Receive Poll
Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when
the next recognized incoming frame is received. This bit is set only when the previous Receive
Descriptor is owned by the DMA. (R/SS/WC)
RECV_INT This bit indicates that the frame reception is complete. When reception is complete, the
Bit[31] of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific
frame status information is updated in the descriptor. The reception remains in the Running state.
(R/SS/WC)
TRANS_UNDFLOW This bit indicates that the Transmit Buffer had an Underflow during frame trans-
mission. Transmission is suspended and an Underflow Error TDES0[1] is set. (R/SS/WC)
RECV_OVFLOW This bit indicates that the Receive Buffer had an Overflow during frame reception.
If the partial frame is transferred to the application, the overflow status is set in RDES0[11].
(R/SS/WC)
TRANS_JABBER_TO This bit indicates that the Transmit Jabber Timer expired, which happens when
the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the
Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state.
This causes the Transmit Jabber Timeout TDES0[14] flag to assert. (R/SS/WC)
TRANS_BUF_UNAVAIL This bit indicates that the host owns the Next Descriptor in the Transmit List
and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit
Process state transitions. To resume processing Transmit descriptors, the host should change
the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand
command. (R/SS/WC)
TRANS_PROC_STOP This bit is set when the transmission is stopped. (R/SS/WC)
TRANS_INT This bit indicates that the frame transmission is complete. When transmission is com-
plete, Bit[31] (OWN) of TDES0 is reset, and the specific frame status information is updated in
the descriptor. (R/SS/WC)
Espressif Systems
Register 10.6. DMASTATUS_REG (0x0014)
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