Espressif ESP32 Technical Reference Manual page 333

12 I2S Controller (I2S)
31
0 0 0 0 0 0 0
I2S_OUT_TOTAL_EOF_INT_ENA The interrupt enable bit for the
(R/W)
I2S_IN_DSCR_EMPTY_INT_ENA The interrupt enable bit for the
rupt. (R/W)
I2S_OUT_DSCR_ERR_INT_ENA The interrupt enable bit for the
(R/W)
I2S_IN_DSCR_ERR_INT_ENA The interrupt enable bit for the
(R/W)
I2S_OUT_EOF_INT_ENA The interrupt enable bit for the
I2S_OUT_DONE_INT_ENA The interrupt enable bit for the
I2S_IN_SUC_EOF_INT_ENA The interrupt enable bit for the
I2S_IN_DONE_INT_ENA The interrupt enable bit for the
I2S_TX_HUNG_INT_ENA The interrupt enable bit for the
I2S_RX_HUNG_INT_ENA The interrupt enable bit for the
I2S_TX_REMPTY_INT_ENA The interrupt enable bit for the
I2S_TX_WFULL_INT_ENA The interrupt enable bit for the
I2S_RX_REMPTY_INT_ENA The interrupt enable bit for the
I2S_RX_WFULL_INT_ENA The interrupt enable bit for the
I2S_TX_PUT_DATA_INT_ENA The interrupt enable bit for the
(R/W)
I2S_RX_TAKE_DATA_INT_ENA The interrupt enable bit for the
(R/W)
Espressif Systems
Register 12.6. I2S_INT_ENA_REG (0x0014)
17
0 0 0 0 0 0 0 0
Submit Documentation Feedback
16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
I2S_OUT_TOTAL_EOF_INT
I2S_IN_DSCR_EMPTY_INT
I2S_OUT_DSCR_ERR_INT
I2S_IN_DSCR_ERR_INT
I2S_OUT_EOF_INT
I2S_OUT_DONE_INT
I2S_IN_SUC_EOF_INT
I2S_IN_DONE_INT
I2S_TX_HUNG_INT
I2S_RX_HUNG_INT
I2S_TX_REMPTY_INT
I2S_TX_WFULL_INT
I2S_RX_REMPTY_INT
I2S_RX_WFULL_INT
I2S_TX_PUT_DATA_INT
I2S_RX_TAKE_DATA_INT
333
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
interrupt.
inter-
interrupt.
interrupt.
interrupt. (R/W)
interrupt. (R/W)
interrupt. (R/W)
interrupt. (R/W)
interrupt. (R/W)
interrupt. (R/W)
interrupt. (R/W)
interrupt. (R/W)
interrupt. (R/W)
interrupt. (R/W)
interrupt.
interrupt.
ESP32 TRM (Version 5.2)
0
0 Reset