Espressif ESP32 Technical Reference Manual page 328

12 I2S Controller (I2S)
I2S_LC_CONF_REG
I2S_RXEOF_NUM_REG
I2S_OUT_LINK_REG
I2S_IN_LINK_REG
I2S_OUT_EOF_DES_ADDR_REG
I2S_IN_EOF_DES_ADDR_REG
I2S_OUT_EOF_BFR_DES_ADDR_REG
I2S_INLINK_DSCR_REG
I2S_INLINK_DSCR_BF0_REG
I2S_INLINK_DSCR_BF1_REG
I2S_OUTLINK_DSCR_REG
I2S_OUTLINK_DSCR_BF0_REG
I2S_OUTLINK_DSCR_BF1_REG
I2S_LC_STATE0_REG
I2S_LC_STATE1_REG
Pulse density (DE) modulation registers
I2S_PDM_CONF_REG
I2S_PDM_FREQ_CONF_REG
Interrupt registers
I2S_INT_RAW_REG
I2S_INT_ST_REG
I2S_INT_ENA_REG
I2S_INT_CLR_REG
Espressif Systems
DMA configuration register
Receive data count
DMA transmit linked list configu-
ration and address
DMA receive linked list configu-
ration and address
The address of transmit link de-
scriptor producing EOF
The address of receive link de-
scriptor producing EOF
The address of transmit buffer
producing EOF
The address of current inlink de-
scriptor
The address of next inlink de-
scriptor
The address of next inlink data
buffer
The address of current outlink
descriptor
The address of next outlink de-
scriptor
The address of next outlink data
buffer
DMA receive status
DMA transmit status
PDM configuration
PDM frequencies
Raw interrupt status
Masked interrupt status
Interrupt enable bits
Interrupt clear bits
328
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0x3FF4F060 0x3FF6D060 R/W
0x3FF4F024 0x3FF6D024 R/W
0x3FF4F030 0x3FF6D030 R/W
0x3FF4F034 0x3FF6D034 R/W
0x3FF4F038 0x3FF6D038 RO
0x3FF4F03C 0x3FF6D03C RO
0x3FF4F040 0x3FF6D040 RO
0x3FF4F048 0x3FF6D048 RO
0x3FF4F04C 0x3FF6D04C RO
0x3FF4F050 0x3FF6D050 RO
0x3FF4F054 0x3FF6D054 RO
0x3FF4F058 0x3FF6D058 RO
0x3FF4F05C 0x3FF6D05C RO
0x3FF4F06C 0x3FF6D06C RO
0x3FF4F070 0x3FF6D070 RO
0x3FF4F0B4 0x3FF6D0B4 R/W
0x3FF4F0B8 0x3FF6D0B8 R/W
0x3FF4F00C 0x3FF6D00C RO
0x3FF4F010 0x3FF6D010 RO
0x3FF4F014 0x3FF6D014
0x3FF4F018 0x3FF6D018
ESP32 TRM (Version 5.2)
R/W
WO