Espressif ESP32 Technical Reference Manual page 45

3 Reset and Clock
3.2.6 RTC Clock
The clock sources of RTC_SLOW_CLK and RTC_FAST_CLK are low-frequency clocks. The RTC module can
operate when most other clocks are stopped.
RTC_SLOW_CLK is used to clock the Power Management module. It can be sourced from RC_SLOW_CLK,
XTL32K_CLK or RC_FAST_DIV_CLK.
RTC_FAST_CLK is used to clock the On-chip Sensor module. It can be sourced from a divided XTL_CLK or from
RC_FAST_CLK.
3.2.7 Audio PLL
The operation of audio and other time-critical data-transfer applications requires highly-configurable, low-jitter,
and accurate clock sources. The clock sources derived from system clocks that serve digital peripherals may
carry jitter and, therefore, they do not support a high-precision clock frequency setting.
Providing an integrated precision clock source can minimize system cost. To this end, ESP32 integrates an
audio PLL. The Audio PLL formula is as follows:
The parameters of this formula are defined below:
• f
: the frequency of the crystal oscillator, usually 40 MHz;
xtal
• sdm0: the value is 0 ~ 255;
• sdm1: the value is 0 ~ 255;
• sdm2: the value is 0 ~ 63;
• odiv: the value is 0 ~ 31;
The operating frequency range of the numerator is 350 MHz ~ 500 MHz:
Please note that sdm1 and sdm0 are not available on revision0 of ESP32. Please consult the silicon revision in
ECO and Workarounds for Bugs in ESP32
Audio PLL can be manually enabled or disabled via registers RTC_CNTL_PLLA_FORCE_PU and RTC_CNTL_PLLA
_FORCE_PD, respectively. Disabling it takes priority over enabling it. When RTC_CNTL_PLLA_FORCE_PU and
RTC_CNTL_PLLA_FORCE_PD are 0, PLL will follow the state of the system, i.e., when the system enters sleep
mode, PLL will be disabled automatically; when the system wakes up, PLL will be enabled automatically.
3.3 Register Summary
The addresses in this section are relative to the SYSCON base address provided in Table
Mapping in Chapter 1 System and
Name
Configuration register
SYSCON_SYSCLK_CONF_REG
SYSCON_XTAL_TICK_CONF_REG
Espressif Systems
f (sdm2 +
xtal
f =
out
350M Hz < f (sdm2 +
xtal
for further details.
Memory.
Description
Configures system clock frequency
Configures the divider value of REF_TICK
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sdm1 sdm0
+ 4)
+
8 16
2 2
2(odiv + 2)
sdm1 sdm0
+ 4) < 500M Hz
+
8 16
2 2
45
1-6 Peripheral Address
Address Access
0x0000 R/W
0x0004 R/W
ESP32 TRM (Version 5.2)