Espressif ESP32 Technical Reference Manual page 512

18 Timer Group (TIMG)
to the register TIMGn_Tx_
LOAD_REG; this will cause the counter value to change instantly. Software can also change the direction of the
time-base counter instantly by changing the value of TIMGn_Tx_INCREASE.
The time-base counter can also be read by software, but because the counter is 64-bit, the CPU can only get the
value as two 32-bit values, the counter value needs to be latched onto TIMGn_TxLO_REG and TIMGn_TxHI_REG
first. This is done by writing any value to TIMGn_TxUPDATE_REG; this will instantly latch the 64-bit timer value
onto the two registers. Software can then read them at any point in time. This approach stops the timer
value being read erroneously when a carry-over happens between reading the low and high word of the timer
value.
18.2.3 Alarm Generation
The timer can trigger an alarm, which can cause a reload and/or an interrupt to occur. The alarm is triggered when
the alarm registers TIMGn_Tx_ALARMLO_REG and TIMGn_Tx_ALARMHI_REG match the current timer value. In
order to simplify the scenario where these registers are set 'too late' and the counter has already passed these
values, the alarm also triggers when the current timer value is higher (for an up-counting timer) or lower (for a
down-counting timer) than the current alarm value: if this is the case, the alarm will be triggered immediately
upon loading the alarm registers. The timer alarm enable bit is automatically cleared once an alarm occurs.
18.2.4 MWDT
Each timer module also contains a Main System Watchdog Timer and its associated registers. While these regis-
ters are described here, their functional description can be found in the chapter entitled
18.2.5 Interrupts
• TIMGn_INT_WDT_INT: Generated when a watchdog timer interrupt stage times out.
• TIMGn_INT_T1_INT: An alarm event on timer 1 generates this interrupt.
• TIMGn_INT_T0_INT: An alarm event on timer 0 generates this interrupt.
18.3 Register Summary
Name
Timer 0 configuration and control registers
TIMGn_T0CONFIG_REG
TIMGn_T0LO_REG
TIMGn_T0HI_REG
TIMGn_T0UPDATE_REG
TIMGn_T0ALARMLO_REG
TIMGn_T0ALARMHI_REG
TIMGn_T0LOADLO_REG
TIMGn_T0LOADHI_REG
TIMGn_T0LOAD_REG
Timer 1 configuration and control registers
TIMGn_T1CONFIG_REG
TIMGn_T1LO_REG
Espressif Systems
Description
Timer 0 configuration register
Timer 0 current value, low 32 bits
Timer 0 current value, high 32 bits
Write to copy current timer value to
TIMGn_T0_(LO/HI)_REG
Timer 0 alarm value, low 32 bits
Timer 0 alarm value, high bits
Timer 0 reload value, low 32 bits
Timer 0 reload value, high 32 bits
Write to reload timer
TIMGn_T0_(LOADLOLOADHI)_REG
Timer 1 configuration register
Timer 1 current value, low 32 bits
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Watchdog
TIMG0 TIMG1
0x3FF5F000 0x3FF60000 R/W
0x3FF5F004 0x3FF60004 RO
0x3FF5F008 0x3FF60008 RO
0x3FF5F00C 0x3FF6000C WO
0x3FF5F010 0x3FF60010 R/W
0x3FF5F014 0x3FF60014 R/W
0x3FF5F018 0x3FF60018 R/W
0x3FF5F01C 0x3FF6001C R/W
from
0x3FF5F020 0x3FF60020 WO
0x3FF5F024 0x3FF60024 R/W
0x3FF5F028 0x3FF60028 RO
ESP32 TRM (Version 5.2)
Timer.
Acc