Espressif ESP32 Technical Reference Manual page 617

27 Memory Management and Protection Units (MMU, MPU)
transfers from memory regions with sensitive data in them.
For each 8 KB region in the SRAM1 and SRAM2 regions, there is a bit in the DPORT_AHB_MPU_TABLE_n_REG
registers which tells the MPU to either allow or disallow DMA access to this region. The DMA MPU uses only
these bits to decide if a DMA transfer can be started; the PID of the process is not a factor. This means that
when the OS wants to restrict its processes in a heterogenous fashion, it will need to re-load these registers
with the values applicable to the process to be run on every context switch.
The register bits that govern access to the 8 KB regions are detailed in Table 27-8. When a register bit is set,
DMA can read/write the corresponding 8 KB memory range. When the bit is cleared, access to that memory
range is denied.
Size
Low
8 KB 0x3FFA_E000
8 KB 0x3FFB_0000
8 KB 0x3FFB_2000
8 KB 0x3FFB_4000
8 KB 0x3FFB_6000
8 KB 0x3FFB_8000
8 KB 0x3FFB_A000
8 KB 0x3FFB_C000
8 KB 0x3FFB_E000
8 KB 0x3FFC_0000
8 KB 0x3FFC_2000
8 KB 0x3FFC_4000
8 KB 0x3FFC_6000
8 KB 0x3FFC_8000
8 KB 0x3FFC_A000
8 KB 0x3FFC_C000
8 KB 0x3FFC_E000
8 KB 0x3FFD_0000
8 KB 0x3FFD_2000
8 KB 0x3FFD_4000
8 KB 0x3FFD_6000
8 KB 0x3FFD_8000
8 KB 0x3FFD_A000
8 KB 0x3FFD_C000
8 KB 0x3FFD_E000
8 KB 0x3FFE_0000
8 KB 0x3FFE_2000
8 KB 0x3FFE_4000
8 KB 0x3FFE_6000
Espressif Systems
Table 27-8. MPU for DMA
Boundary address
High
Internal SRAM 2
0x3FFA_FFFF
0x3FFB_1FFF
0x3FFB_3FFF
0x3FFB_5FFF
0x3FFB_7FFF
0x3FFB_9FFF
0x3FFB_BFFF
0x3FFB_DFFF
0x3FFB_FFFF
0x3FFC_1FFF
0x3FFC_3FFF
0x3FFC_5FFF
0x3FFC_7FFF
0x3FFC_9FFF
0x3FFC_BFFF
0x3FFC_DFFF
0x3FFC_FFFF
0x3FFD_1FFF
0x3FFD_3FFF
0x3FFD_5FFF
0x3FFD_7FFF
0x3FFD_9FFF
0x3FFD_BFFF
0x3FFD_DFFF
0x3FFD_FFFF
Internal SRAM 1
0x3FFE_1FFF
0x3FFE_3FFF
0x3FFE_5FFF
0x3FFE_7FFF
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Register
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
DPORT_AHB_MPU_TABLE_0_REG
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Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ESP32 TRM (Version 5.2)