Espressif ESP32 Technical Reference Manual page 96

5 DPort Registers
5.4 Register Summary
Name
System and memory registers
DPORT_PRO_BOOT_REMAP_CTRL_REG
DPORT_APP_BOOT_REMAP_CTRL_REG
DPORT_CACHE_MUX_MODE_REG
Reset and clock registers
DPORT_CPU_PER_CONF_REG
Interrupt matrix registers
DPORT_CPU_INTR_FROM_CPU_0_REG
DPORT_CPU_INTR_FROM_CPU_1_REG
DPORT_CPU_INTR_FROM_CPU_2_REG
DPORT_CPU_INTR_FROM_CPU_3_REG
DPORT_PRO_INTR_STATUS_REG_0_REG
DPORT_PRO_INTR_STATUS_REG_1_REG
DPORT_PRO_INTR_STATUS_REG_2_REG
DPORT_APP_INTR_STATUS_REG_0_REG
DPORT_APP_INTR_STATUS_REG_1_REG
DPORT_APP_INTR_STATUS_REG_2_REG
DPORT_PRO_MAC_INTR_MAP_REG
DPORT_PRO_MAC_NMI_MAP_REG
DPORT_PRO_BB_INT_MAP_REG
DPORT_PRO_BT_MAC_INT_MAP_REG
DPORT_PRO_BT_BB_INT_MAP_REG
DPORT_PRO_BT_BB_NMI_MAP_REG
DPORT_PRO_RWBT_IRQ_MAP_REG
DPORT_PRO_RWBLE_IRQ_MAP_REG
DPORT_PRO_RWBT_NMI_MAP_REG
DPORT_PRO_RWBLE_NMI_MAP_REG
DPORT_PRO_SLC0_INTR_MAP_REG
DPORT_PRO_SLC1_INTR_MAP_REG
DPORT_PRO_UHCI0_INTR_MAP_REG
DPORT_PRO_UHCI1_INTR_MAP_REG
DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG
DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG
DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG
DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG
DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG
DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG
DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG
DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG
DPORT_PRO_GPIO_INTERRUPT_MAP_REG
DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG
Espressif Systems
Description
remap mode for PRO_CPU
remap mode for APP_CPU
the mode of the two caches
sharing the memory
Selects CPU clock
interrupt 0 in both CPUs
interrupt 1 in both CPUs
interrupt 2 in both CPUs
interrupt 3 in both CPUs
PRO_CPU interrupt status 0
PRO_CPU interrupt status 1
PRO_CPU interrupt status 2
APP_CPU interrupt status 0
APP_CPU interrupt status 1
APP_CPU interrupt status 2
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96
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Address Access
0x3FF00000 R/W
0x3FF00004 R/W
0x3FF0007C R/W
0x3FF0003C R/W
0x3FF000DC R/W
0x3FF000E0 R/W
0x3FF000E4 R/W
0x3FF000E8 R/W
0x3FF000EC RO
0x3FF000F0 RO
0x3FF000F4 RO
0x3FF000F8 RO
0x3FF000FC RO
0x3FF00100 RO
0x3FF00104 R/W
0x3FF00108 R/W
0x3FF0010C R/W
0x3FF00110 R/W
0x3FF00114 R/W
0x3FF00118 R/W
0x3FF0011C R/W
0x3FF00120 R/W
0x3FF00124 R/W
0x3FF00128 R/W
0x3FF0012C R/W
0x3FF00130 R/W
0x3FF00134 R/W
0x3FF00138 R/W
0x3FF0013C R/W
0x3FF00140 R/W
0x3FF00144 R/W
0x3FF00148 R/W
0x3FF0014C R/W
0x3FF00150 R/W
0x3FF00154 R/W
0x3FF00158 R/W
0x3FF0015C R/W
0x3FF00160 R/W
ESP32 TRM (Version 5.2)