Espressif ESP32 Technical Reference Manual page 31

1 System and Memory
Instruction 0x400C_2000
1.3.4 Cache
As shown in Figure 1-3, each of the two CPUs in ESP32 has 32 KB of cache featuring a block size of 32 bytes for
accessing external storage. PRO CPU uses bit PRO_CACHE_ENABLE in register DPORT_PRO_CACHE_CTRL_REG
to enable the Cache, while APP CPU uses bit APP_CACHE_ENABLE in register DPORT_APP_CACHE_CTRL_REG
to enable the same function.
ESP32 uses a two-way set-associative cache. When the Cache function is to be used either by PRO CPU or APP
CPU, bit CACHE_MUX_MODE[1:0] in register DPORT_CACHE_MUX_MODE_REG can be set to select POOL0 or
POOL1 in the Internal SRAM0 as the cache memory. When both PRO CPU and APP CPU use the Cache function,
POOL0 and POOL1 in the Internal SRAM0 will be used simultaneously as the cache memory, while they can also
be used by the instruction bus. This is depicted in table
CACHE_MUX_MODE
As described in table 1-5, when bit CACHE_MUX_MODE is set to 1 or 2, PRO CPU and APP CPU cannot enable
the Cache function at the same time. When the Cache function is enabled, POOL0 or POOL1 can only be used
as the cache memory, and cannot be used by the instruction bus as well.
ESP32 Cache supports the Flush function. It is worth noting that when the Flush function is used, the data
written in the cache will be disposed rather than being rewritten into the External SRAM. To enable the Flush
function, first clear bit x_CACHE_FLUSH_ENA in register DPORT_x_CACHE_CTRL_REG, then set this bit to 1.
Espressif Systems
0x40BF_FFFF
Figure 1-3. Cache Block Diagram
1-5
Table 1-5. Cache memory mode
POOL0
0 PRO CPU
1 PRO CPU/APP CPU
2 -
3 APP CPU
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11512 KB External Flash
below.
POOL1
APP CPU
-
PRO CPU/APP CPU
PRO CPU
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ESP32 TRM (Version 5.2)