Espressif ESP32 Technical Reference Manual page 54

4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)
4.5.2 Analog Function Description
The RTC function and analog function of RTC_GPIOs can only be selected one at a time. For the RTC_GPIO8 to
RTC_GPIO17 pins, their analog outputs can be directed to the IO_MUX, controlled by the
bit. If the bit is set to 1, the analog output is enabled, allowing the signal to be routed to IO_MUX through analog
function. On the other hand, if the bit is set to 0, the input signal from the pad is output to IO_MUX through
digital function.
4.6 Light-sleep Mode Pin Functions
Pins can have different functions when the ESP32 is in Light-sleep mode. If the SLP_SEL bit in the IO_MUX
register for a GPIO pad is set to 1, a different set of registers is used to control the pad when the ESP32 is in
Light-sleep mode:
IO_MUX Function
Output Drive Strength
Pull-up Resistor
Pull-down Resistor
Output Enable
If SLP_SEL is set to 0, the pin functions remain the same in both normal execution and Light-sleep mode.
4.7 Pad Hold Feature
Each IO pad (including the RTC pads) has an individual hold function controlled by a RTC register. When the pad
is set to hold, the state is latched at that moment and will not change no matter how the internal signals change
or how the IO_MUX configuration or GPIO configuration is modified. Users can use the hold function for the
pads to retain the pad state through a core reset triggered by watchdog time-out or Deep-sleep events.
The Hold state of each pin is controlled by the result of OR operation of the pin's Hold enable signal and the
global Hold enable signal.
• Digital Pins (GPIO18 ~ GPIO19, GPIO21 ~ GPIO23, GPIO25 ~ GPIO27, GPIO32 ~ GPIO39)
– RTCIO_DIG_PAD_HOLD_REG[n], controls the Hold enable signal of each digital pin. See Table
the bit mapping for the pins.
– RTC_CNTL_DG_PAD_FORCE_HOLD, controls the global Hold signal of all digital pins.
To use this feature, follow the steps below:
– To maintain the pin's input/output status in Deep-sleep, set
31) before power off. See Table
each pin after the chip is woken up, clear the bits above.
– Alternatively, set
RTC_CNTL_DG_PAD_FORCE_UNHOLD
• RTC Pins (GPIO0 ~ GPIO17)
Espressif Systems
Table 4-1. IO_MUX Light-sleep Pin Function Registers
Normal Execution
OR SLP_SEL = 0
FUN_DRV
FUN_WPU
FUN_WPD
(From GPIO Matrix _OEN field)
4-8 for the bit mapping for the pins. To disable the Hold function of
RTC_CNTL_DG_PAD_FORCE_HOLD
to disable the hold function of all digital pins.
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Light-sleep Mode
AND SLP_SEL = 1
MCU_DRV
MCU_WPU
MCU_WPD
MCU_OE
RTCIO_DIG_PAD_HOLD_REG[n]
to hold the values of all digital pins, or set
54
RTC_IO_TOUCH_PADn/m_TO_GPIO
4-8 for
(n = 0 ~
ESP32 TRM (Version 5.2)