Philips Standard - Espressif ESP32 Technical Reference Manual

12 I2S Controller (I2S)
In master transmitting mode, "M", whose value is >=2, is the I2S_TX_BCK_DIV_NUM[5:0] bit of register I2S_SAMPLE
_RATE_CONF_REG. In master receiving mode, "M" is the I2S_RX_BCK_DIV_NUM[5:0] bit of register I2S_SAMPLE
_RATE_CONF_REG.
12.4 I2S Mode
The ESP32 I2S module integrates an A-law compression/decompression module to enable compression/decompression
of the received audio data. The RX_PCM_BYPASS bit and the TX_PCM_BYPASS bit of register I2S_CONF1_REG
should be cleared when using the A-law compression/decompression module.
12.4.1 Supported Audio Standards
In the I2S bus, BCK is the serial clock, WS is the left- /right-channel selection signal (also called word select
signal), and SD is the serial data signal for transmitting/receiving digital audio data. WS and SD signals in the
I2S module change on the falling edge of BCK, while the SD signal can be sampled on the rising edge of BCK.
If the I2S_RX_RIGHT_FIRST bit and the I2S_TX_RIGHT_FIRST bit of register I2S_CONF_REG are set to 1, the I2S
module is configured to receive and transmit right-channel data first. Otherwise, the I2S module receives and
transmits left-channel data first.

12.4.1.1 Philips Standard

Figure 12-3. Philips Standard
As is shown in Figure 12-3, the Philips I2S bus specifications require that the WS signal starts to change one
BCK clock cycle earlier than the SD signal on BCK falling edge, which means the WS signal becomes valid one
clock cycle before the first bit of data transfer on the current channel, and changes one clock cycle earlier than
the end of data transfer on the current channel. The SD signal line transmits the most significant bit of audio
data first. If the I2S_RX_MSB_SHIFT bit and the I2S_TX_MSB_SHIFT bit of register I2S_CONF_REG are set to 1,
respectively, the I2S module will use the Philips standard when receiving and transmitting data.
Espressif Systems 316 ESP32 TRM (Version 5.2)
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