Espressif ESP32 Technical Reference Manual page 624

27 Memory Management and Protection Units (MMU, MPU)
• For the APP_CPU, MMU entry 3200 needs to be set to 0x40 and marked as valid by clearing the 8'th bit.
Thus, 0x040 is written to MMU entry 3200.
• Now, the PRO_CPU and the APP_CPU can access different physical memory regions through the same
virtual address.
27.3.2.3 Peripheral
The Peripheral MPU manages the 39 peripheral modules. This MMU can be configured per peripheral to only
allow access from a process with a certain PID. The registers to configure this are detailed in Table 27-19.
Peripheral
DPort Register
AES Accelerator
RSA Accelerator
SHA Accelerator
Secure Boot
Cache MMU Table
PID Controller
UART0
SPI1
SPI0
GPIO
RTC
IO MUX
SDIO Slave
UDMA1
I2S0
UART1
I2C0
UDMA0
SDIO Slave
RMT
PCNT
SDIO Slave
LED PWM
Efuse Controller
Flash Encryption
PWM0
TIMG0
TIMG1
SPI2
SPI3
SYSCON
Espressif Systems
Table 27-19. MPU for Peripheral
PID = 0/1 PID = 2 ~ 7
Access Forbidden
Access Forbidden
Access Forbidden
Access Forbidden
Access Forbidden
Access Forbidden
Access Forbidden
Access DPORT_AHBLITE_MPU_TABLE_UART_REG
Access DPORT_AHBLITE_MPU_TABLE_SPI1_REG
Access DPORT_AHBLITE_MPU_TABLE_SPI0_REG
Access DPORT_AHBLITE_MPU_TABLE_GPIO_REG
Access DPORT_AHBLITE_MPU_TABLE_RTC_REG
Access DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG
Access DPORT_AHBLITE_MPU_TABLE_HINF_REG
Access DPORT_AHBLITE_MPU_TABLE_UHCI1_REG
Access DPORT_AHBLITE_MPU_TABLE_I2S0_REG
Access DPORT_AHBLITE_MPU_TABLE_UART1_REG
Access DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG
Access DPORT_AHBLITE_MPU_TABLE_UHCI0_REG
Access DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG
Access DPORT_AHBLITE_MPU_TABLE_RMT_REG
Access DPORT_AHBLITE_MPU_TABLE_PCNT_REG
Access DPORT_AHBLITE_MPU_TABLE_SLC_REG
Access DPORT_AHBLITE_MPU_TABLE_LEDC_REG
Access DPORT_AHBLITE_MPU_TABLE_EFUSE_REG
Access DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG
Access DPORT_AHBLITE_MPU_TABLE_PWM0_REG
Access DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG
Access DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG
Access DPORT_AHBLITE_MPU_TABLE_SPI2_REG
Access DPORT_AHBLITE_MPU_TABLE_SPI3_REG
Access DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG
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