Espressif ESP32 Technical Reference Manual page 127

7 SPI Controller (SPI)
7 SPI Controller (SPI)
7.1 Overview
As Figure 7-1 shows, ESP32 integrates four SPI controllers which can be used to communicate with external
devices that use the SPI protocol. Controller SPI0 is used as a buffer for accessing external memory. Controller
SPI1 can be used as a master. Controllers SPI2 and SPI3 can be configured as either a master or a slave. When
used as a master, each SPI controller can drive multiple CS signals (CS0~CS2) to activate multiple slaves.
Controllers SPI1~SPI3 share two DMA channels.
The SPI signal buses consist of D, Q, CS0-CS2, CLK, WP, and HD signals, as Table
and SPI1 share one signal bus through an arbiter; the signals of the shared bus start with "SPI". Controllers SPI2
and SPI3 use signal buses starting with "HSPI" and "VSPI" respectively. The I/O lines included in the above-
mentioned signal buses can be mapped to pins via either the IO_MUX module or the GPIO matrix. (Please refer
to Chapter IO_MUX for details.)
The SPI controller supports four-line full-duplex/half-duplex communication (MOSI, MISO, CS, and CLK lines)
and three-line half-duplex-only communication (DATA, CS, and CLK lines) in GP-SPI mode. In QSPI mode, an
SPI controller accesses the flash or SRAM by using signal buses D, Q, CS0~CS2, CLK, WP, and HD as a four-bit
parallel SPI bus. The mapping between SPI bus signals and pin function signals under different communication
modes is shown in Table 7-1.
Table 7-1. Mapping Between SPI Bus Signals and Pin Function Signals
Four-line GP-SPI Three-line GP-SPI
Full-duplex/half- Half-duplex signal
duplex signal bus bus
MOSI DATA
MISO -
CS CS
CLK CLK
- -
- -
Espressif Systems
Figure 7-1. SPI Architecture
QSPI
Signal bus
D
Q
CS
CLK
WP
HD
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7-1 shows. Controllers SPI0
Pin function signals
SPI signal HSPI signal
bus bus
SPID HSPID
SPIQ HSPIQ
SPICS0 HSPICS0
SPICLK HSPICLK
SPIWP HSPIWP
SPIHD HSPIHD
ESP32 TRM (Version 5.2)
VSPI signal
bus
VSPID
VSPIQ
VSPICS0
VSPICLK
VSPIWP
VSPIHD