Espressif ESP32 Technical Reference Manual page 589

23 SHA Accelerator (SHA)
23 SHA Accelerator (SHA)
23.1 Introduction
The SHA Accelerator is included to speed up SHA hashing operations significantly, compared to SHA hashing
algorithms implemented solely in software. The SHA Accelerator supports four algorithms of FIPS PUB 180-4,
specifically SHA-1, SHA-256, SHA-384 and SHA-512.
23.2 Features
Hardware support for popular secure hashing algorithms:
• SHA-1
• SHA-256
• SHA-384
• SHA-512
23.3 Functional Description
23.3.1 Padding and Parsing the Message
The SHA Accelerator can only accept one message block at a time. Software divides the message into blocks
according to "5.2 Parsing the Message" in FIPS PUB 180-4 and writes one block to the SHA_TEXT_n_REG
registers each time. For SHA-1 and SHA-256, software writes a 512-bit message block to SHA_TEXT_0_REG
~ SHA_TEXT_15_REG each time. For SHA-384 and SHA-512, software writes a 1024-bit message block to
SHA_TEXT_0_REG ~ SHA_TEXT_31_REG each time.
The SHA Accelerator is unable to perform the padding operation of "5.1 Padding the Message" in FIPS PUB
180-4; Note that the user software is expected to pad the message before feeding it into the accelerator.
As described in "2.2.1: Parameters" in FIPS PUB 180-4, "M
is stored in SHA_TEXT_0_REG. In the same fashion, the SHA_TEXT_1_REG register stores the second left-most
word of a message block M
23.3.2 Message Digest
When the hashing operation is finished, the message digest will be refreshed by SHA Accelerator and will
be stored in SHA_TEXT_n_REG. SHA-1 produces a 160-bit message digest and stores it in SHA_TEXT_0_REG ~
SHA_TEXT_4_REG. SHA-256 produces a 256-bit message digest and stores it in SHA_TEXT_0_REG ~ SHA_TEXT_7_REG.
SHA-384 produces a 384-bit message digest and stores it in SHA_TEXT_0_REG ~ SHA_TEXT_11_REG. SHA-512
produces a 512-bit message digest and stores it in SHA_TEXT_0_REG ~ SHA_TEXT_15_REG.
As described in "2.2.1 Parameters" in FIPS PUB 180-4, "H
message digest", while "H
digest is stored in SHA_TEXT_0_REG. In the same fashion, the second leftmost word H
digest is stored in SHA_TEXT_1_REG, etc.
23.3.3 Hash Operation
There is a set of control registers for SHA-1, SHA-256, SHA-384 and SHA-512, respectively; different hashing
algorithms use different control registers.
Espressif Systems
(N )
, etc.
1
(i)
is the leftmost word of hash value i", so the leftmost word H
0
Submit Documentation Feedback
(i)
is the leftmost word of message block i". M
0
(N )
is the final hash value, and is used to determine the
589
(i)
0
(N )
in the message
0
(N )
in the message
1
ESP32 TRM (Version 5.2)