Espressif ESP32 Technical Reference Manual page 629

28 Process ID Controller (PID)
Figure 28-1. Interrupt Nesting
step 5.
In step 6, after the values of register PIDCTRL_PID_CONFIRM_REG and register PIDCTRL_NMI_MASK_DISABLE_REG
are set to 1, PID Controller will not immediately switch PID to the value of register PIDCTRL_PID_NEW_REG, nor
disable CPU NMI Interrupt Mask signal at once. Instead, PID Controller performs each task after a different num-
ber of clock cycles. The numbers of clock cycles are the values specified in register PIDCTRL_PID_DELAY_REG
and PIDCTRL_NMI_DELAY_REG respectively.
Espressif Systems 629 ESP32 TRM (Version 5.2)
Submit Documentation Feedback