Espressif ESP32 Technical Reference Manual page 669

30 ULP Coprocessor (ULP)
ALU_sel Instruction
0 STAGE_INC
1 STAGE_DEC
2 STAGE_RST
30.4.2 ST – Store Data in Memory
31 28 27
4'd6 3'b100
Operand Description - see Figure
Offset 10-bit signed value, offset expressed in 32-bit words
Rsrc Register R[0-3], 16-bit value to store
Rdst Register R[0-3], address of the destination, expressed in 32-bit words
Description
The instruction stores the 16-bit value of Rsrc in the lower half-word of memory with address Rdst + Offset.
The upper half-word is written with the current program counter (PC) (expressed in words and shifted to the
left by 5 bits) OR'd with Rdst (0..3):
Mem [ Rdst + Offset ]{31:0} = {PC[10:0], 3'b0, Rdst, Rsrc[15:0]}
The application can use the higher 16 bits to determine which instruction in the ULP program has written any
particular word into memory.
Note:
• This instruction can only access 32-bit memory words.
• Data from Rsrc is always stored in the lower 16 bits of a memory word. Differently put, it is not possible to
store Rsrc in the upper 16 bits of memory.
• The "Mem" written is the RTC_SLOW_MEM memory. Address 0, as seen by the ULP coprocessor,
corresponds to address 0x50000000, as seen by the main CPUs.
30.4.3 LD – Load Data from Memory
31 28
4'd13
Operand Description - see Figure
Offset 10-bit signed value, offset expressed in 32-bit words
Rsrc Register R[0-3], address of destination memory, expressed in 32-bit words
Rdst Register R[0-3], destination
Description
Espressif Systems
Operation
Stage_cnt = Stage_cnt + Imm
Stage_cnt = Stage_cnt - Imm
Stage_cnt = 0
Table 30-3. ALU Operations with Stage Count Register
25 20
4'b0
Figure 30-6. Instruction Type — ST
30-6
20
Figure 30-7. Instruction Type — LD
30-7
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Description
Increment stage count register
Decrement stage count register
Reset stage count register
10
Offset
10
Offset
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3 2 1 0
Rdst Rsrc
6'b0
3 2 1 0
Rsrc Rdst
ESP32 TRM (Version 5.2)