Espressif ESP32 Technical Reference Manual page 17

List of Tables
11-1 SCL Frequency Configuration
12-1 I2S Signal Bus Description
12-2 Register Configuration
12-3 Send Channel Mode
12-4 Modes of Writing Received Data into FIFO and the Corresponding Register Configuration
12-5 The Register Configuration to Which the Four Modes Correspond
12-6 Upsampling Rate Configuration
12-7 Down-sampling Configuration
14-1 Commonly-used Frequencies and Resolutions
16-1 Configuration Parameters of the Operator Submodule
16-2 Timing Events Used in PWM Generator
16-3 Timing Events Priority When PWM Timer Increments
16-4 Timing Events Priority when PWM Timer Decrements
16-5 Dead Time Generator Switches Control Registers
16-6 Typical Dead Time Generator Operating Modes
20-1 System Parameters
20-2 BLOCK1/2/3 Encoding
20-3 Program Registers
20-4 Timing Configuration
20-5 Software Read Registers
21-1 Data Frames and Remote Frames in SFF and EFF
21-2 Error Frame
21-3 Overload Frame
21-4 Interframe Space
21-5 Segments of a Nominal Bit Time
21-6 Bit Information of TWAI_CLOCK_DIVIDER_REG; TWAI Address 0x18
21-7 Bit Information of TWAI_BUS_TIMING_1_REG; TWAI Address 0x1c
21-8 Buffer Layout for Standard Frame Format and Extended Frame Format
21-9 TX/RX Frame Information (SFF/EFF); TWAI Address 0x40
21-10 TX/RX Identifier 1 (SFF); TWAI Address 0x44
21-11 TX/RX Identifier 2 (SFF); TWAI Address 0x48
21-12 TX/RX Identifier 1 (EFF); TWAI Address 0x44
21-13 TX/RX Identifier 2 (EFF); TWAI Address 0x48
21-14 TX/RX Identifier 3 (EFF); TWAI Address 0x4c
21-15 TX/RX Identifier 4 (EFF); TWAI Address 0x50
21-16 Bit Information of TWAI_ERR_CODE_CAP_REG; TWAI Address 0x30
21-17 Bit Information of Bits SEG.4 - SEG.0
21-18 Bit Information of TWAI_ARB LOST CAP_REG; TWAI Address 0x2c
22-1 Operation Mode
22-2 AES Text Endianness
22-3 AES-128 Key Endianness
22-4 AES-192 Key Endianness
22-5 AES-256 Key Endianness
27-1 MPU and MMU Structure for Internal Memory
27-2 MPU for RTC FAST Memory
27-3 MPU for RTC SLOW Memory
Espressif Systems 17
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ESP32 TRM (Version 5.2)