Espressif ESP32 Technical Reference Manual page 510

17 Pulse Count Controller (PCNT)
31
0x0000
PCNT_CLK_EN Configures register clock gating.
0: Support clock only when the application writes registers.
1: Always force the clock on for registers.
(R/W)
PCNT_CNT_PAUSE_Un
PCNT_PLUS_CNT_RST_Un
Register 17.10. PCNT_Un_STATUS_REG (n: 0-7) (0x90+0x0C*n)
31
0 0 0 0 0 0 0
PCNT_THR_ZERO_LAT_Un
PCNT_THR_H_LIM_LAT_Un
(RO)
PCNT_THR_L_LIM_LAT_Un
(RO)
PCNT_THR_THRES0_LAT_Un
(RO)
PCNT_THR_THRES1_LAT_Un
PCNT_THR_ZERO_MODE_Un
value is +0 (the counter values are represented by signed binary numbers); 1: counting value is
-0; 2: counting value is negative; 3: counting value is positive. (RO)
Espressif Systems
Register 17.9. PCNT_CTRL_REG (0x00b0)
17
Set this bit to freeze unit n's counter. (R/W)
Set this bit to clear unit n's counter. (R/W)
0 0 0 0 0 0 0 0
The last interrupt happened on counter for unit
The last interrupt happened on counter for unit
The last interrupt happened on counter for unit
The last interrupt happened on counter for unit
The last interrupt happened on counter for unit
This register stores the current status of the counter. 0: counting
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16 15 14 13 12 11 10 9
0 0 1 0 1 0 1 0
0 0 0 0 0 0 0 0
510
8 7 6 5 4 3 2 1
1 0 1 0 1 0 1 0
7 6 5 4 3 2 1
0 0 0 0 0 0 0 00
n reaching 0. (RO)
n reaching thr_h_lim.
n reaching thr_l_lim.
n reaching thres0.
n reaching thres1. (RO)
ESP32 TRM (Version 5.2)
0
1 Reset
0
Reset