Espressif ESP32 Technical Reference Manual page 614

27 Memory Management and Protection Units (MMU, MPU)
CPU VIRTUAL
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3FFC_2345
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PAGE 15
Table 27-4. Page Mode of MMU for the Remaining 128 KB of Internal SRAM0 and SRAM2
DPORT_IMMU_PAGE_MODE
0
1
2
Non-MMU Governed Memory
For the MMU-managed region of SRAM0 and SRAM2, the page size is configurable as 8 KB, 4 KB and 2 KB. The
configuration is done by setting the DPORT_IMMU_PAGE_MODE (for SRAM0) and DPORT_DMMU_PAGE_MODE
(for SRAM2) bits in registers DPORT_IMMU_PAGE_MODE_REG and DPORT_DMMU_PAGE_MODE_REG, as de-
tailed in Table 27-4. Because the number of pages for either region is fixed at 16, the total amount of memory
covered by these pages is 128 KB when 8 KB pages are selected, 64 KB when 4 KB pages are selected, and 32
KB when 2 KB pages are selected. This implies that for 8 KB pages, the entire MMU-managed range is used, but
for the other page sizes there will be a part of the 128 KB memory that will not be governed by the MMU settings.
Concretely, for a page size of 4 KB, these regions are 0x4009_0000 to 0x4009_FFFF and 0x3FFD_0000 to
0x3FFD_FFFF; for a page size of 2 KB, the regions are 0x4008_8000 to 0x4009_FFFF and 0x3FFC_8000 to
0x3FFD_FFFF. These ranges are readable and writable by processes with a PID of 0 or 1; processes with other
PIDs cannot access this memory.
The layout of the pages in memory space is linear, namely, an SRAM0 MMU page
0x40080000 + (pagesize ∗ n) to 0x40080000 + (pagesize ∗
0x3F F C0000 + (pagesize ∗ n) to 0x3F F C0000 + (pagesize ∗
addresses in full.
Espressif Systems
MMU
3FFC_0000
3FFC_2000
3FFC_4000
3FFC_6000
3FFD_E000
3FFE_0000
Figure 27-1. MMU Access Example
DPORT_DMMU_PAGE_MODE
0
1
2
(n + 1)
+ 1) 1). Tables
(n
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PHYSICAL
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3FFC_4345
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PAGE 15
Page size
8 KB
4 KB
2 KB
n covers address space
1); similarily, an SRAM2 MMU page
27-5 and 27-6
ESP32 TRM (Version 5.2)
3FFC_0000
3FFC_2000
3FFC_4000
3FFC_6000
3FFD_E000
3FFE_0000
n covers
show the resulting