Espressif ESP32 Technical Reference Manual page 356

13 UART Controller (UART)
UART_INT_ST_REG
UART_INT_ENA_REG
UART_INT_CLR_REG
13.4.2 UHCI Register Summary
Name
Configuration registers
UHCI_CONF0_REG
UHCI_CONF1_REG
UHCI_ESCAPE_CONF_REG
UHCI_HUNG_CONF_REG
UHCI_ESC_CONF0_REG
UHCI_ESC_CONF1_REG
UHCI_ESC_CONF2_REG
UHCI_ESC_CONF3_REG
DMA configuration
UHCI_DMA_OUT_LINK_REG
UHCI_DMA_IN_LINK_REG
UHCI_DMA_OUT_PUSH_REG
UHCI_DMA_IN_POP_REG
DMA status
UHCI_DMA_OUT_STATUS_REG
UHCI_DMA_OUT_EOF_DES_ADDR_REG
UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG
UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG
UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG
UHCI_DMA_IN_DSCR_REG
UHCI_DMA_IN_DSCR_BF0_REG
Espressif Systems
Masked interrupt sta-
tus
Interrupt enable bits
Interrupt clear bits
Description
UART and frame separation
config
UHCI config register
Escape characters config-
uration
Timeout configuration
Escape sequence config-
uration register 0
Escape sequence config-
uration register 1
Escape sequence config-
uration register 2
Escape sequence config-
uration register 3
Link descriptor address
and control
Link descriptor address
and control
FIFO data push register
FIFO data pop register
DMA FIFO status
Out EOF link descriptor ad-
dress on success
Out EOF link descriptor ad-
dress on error
In EOF link descriptor ad-
dress on success
In EOF link descriptor ad-
dress on error
Current inlink descriptor,
first word
Current inlink descriptor,
second word
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0x3FF40008 0x3FF50008 0x3FF6E008 RO
0x3FF4000C 0x3FF5000C 0x3FF6E00C R/W
0x3FF40010 0x3FF50010 0x3FF6E010
UDMA0
0x3FF54000 0x3FF4C000 R/W
0x3FF5402C 0x3FF4C02C R/W
0x3FF54064 0x3FF4C064 R/W
0x3FF54068 0x3FF4C068 R/W
0x3FF540B0 0x3FF4C0B0 R/W
0x3FF540B4 0x3FF4C0B4 R/W
0x3FF540B8 0x3FF4C0B8 R/W
0x3FF540BC 0x3FF4C0BC R/W
0x3FF54024 0x3FF4C024 R/W
0x3FF54028 0x3FF4C028 R/W
0x3FF54018 0x3FF4C018 R/W
0x3FF54020 0x3FF4C020 RO
0x3FF54014 0x3FF4C014 RO
0x3FF54038 0x3FF4C038 RO
0x3FF54044 0x3FF4C044 RO
0x3FF5403C 0x3FF4C03C RO
0x3FF54040 0x3FF4C040 RO
0x3FF5404C 0x3FF4C04C RO
0x3FF54050 0x3FF4C050 RO
ESP32 TRM (Version 5.2)
WO
UDMA1 Acc