Espressif ESP32 Technical Reference Manual page 499

16 Motor Control PWM (PWM)
31 30 29 28 27 26 25
0 0 0 0 0 0 0
INT_CAP2_INT_CLR Set this bit to clear interrupt triggered by capture on channel 2. (WO)
INT_CAP1_INT_CLR Set this bit to clear interrupt triggered by capture on channel 1. (WO)
INT_CAP0_INT_CLR Set this bit to clear interrupt triggered by capture on channel 0. (WO)
INT_FH2_OST_INT_CLR Set this bit to clear interrupt triggered by a one-shot mode action on PWM2.
(WO)
INT_FH1_OST_INT_CLR Set this bit to clear interrupt triggered by a one-shot mode action on PWM1.
(WO)
INT_FH0_OST_INT_CLR Set this bit to clear interrupt triggered by a one-shot mode action on PWM0.
(WO)
INT_FH2_CBC_INT_CLR Set this bit to clear interrupt triggered by a cycle-by-cycle mode action on
PWM2. (WO)
INT_FH1_CBC_INT_CLR Set this bit to clear interrupt triggered by a cycle-by-cycle mode action on
PWM1. (WO)
INT_FH0_CBC_INT_CLR Set this bit to clear interrupt triggered by a cycle-by-cycle mode action on
PWM0. (WO)
INT_OP2_TEB_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 2 TEB event.
(WO)
INT_OP1_TEB_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 1 TEB event. (WO)
INT_OP0_TEB_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 0 TEB event.
(WO)
INT_OP2_TEA_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 2 TEA event.
(WO)
INT_OP1_TEA_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 1 TEA event. (WO)
INT_OP0_TEA_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 0 TEA event.
(WO)
INT_FAULT2_CLR_INT_CLR Set this bit to clear interrupt triggered when event_f2 ends. (WO)
INT_FAULT1_CLR_INT_CLR Set this bit to clear interrupt triggered when event_f1 ends. (WO)
INT_FAULT0_CLR_INT_CLR Set this bit to clear interrupt triggered when event_f0 ends. (WO)
INT_FAULT2_INT_CLR Set this bit to clear interrupt triggered when event_f2 starts. (WO)
INT_FAULT1_INT_CLR Set this bit to clear interrupt triggered when event_f1 starts. (WO)
INT_FAULT0_INT_CLR Set this bit to clear interrupt triggered when event_f0 starts. (WO)
INT_TIMER2_TEP_INT_CLR Set this bit to clear interrupt triggered by a PWM timer 2 TEP event. (WO)
Continued on the next page...
Espressif Systems
Register 16.72. INT_CLR_PWM_REG (0x011c)
24 23 22 21 20 19 18 17
0 0 0 0 0 0 0 0
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16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0
499
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
ESP32 TRM (Version 5.2)
0
0
Reset