Espressif ESP32 Technical Reference Manual page 317

12 I2S Controller (I2S)
12.4.1.2 MSB Alignment Standard
Figure 12-4. MSB Alignment Standard
The MSB alignment standard is shown in Figure 12-4. WS and SD signals both change simultaneously on the
falling edge of BCK under the MSB alignment standard. The WS signal continues until the end of the current
channel-data transmission, and the SD signal line transmits the most significant bit of audio data first. If the
I2S_RX_MSB_SHIFT and I2S_TX_MSB_SHIFT bits of register I2S_CONF_REG are cleared, the I2S module will
use the MSB alignment standard when receiving and transmitting data.
12.4.1.3 PCM Standard
As is shown in Figure 12-5, under the short frame synchronization mode of the PCM standard, the WS signal
starts to change a BCK clock cycle earlier than the SD signal, which means that the WS signal takes effect a
clock cycle earlier than the first bit of the current channel-data transmission and continues for one extra BCK
clock cycle. The SD signal line transmits the most significant bit of audio data first. If the I2S_RX_SHORT_SYNC
and I2S_TX_SHORT_SYNC bits of register I2S_CONF_REG are set, the I2S module will receive and transmit data
in the short frame synchronization mode.
Figure 12-5. PCM Standard
12.4.2 Module Reset
The four low-order bits in register I2S_CONF_REG, that is, I2S_TX_RESET, I2S_RX_RESET, I2S_TX_FIFO_RESET
and I2S_RX_FIFO_RESET reset the receive module, the transmit module and the corresponding FIFO buffer,
respectively. In order to finish a reset operation, the corresponding bit should be set and then cleared by
software.
12.4.3 FIFO Operation
The data read/write packet length for a FIFO operation is 32 bits. The data packet format for the FIFO buffer
can be configured using configuration registers. As shown in Figure 12-1, both sent and received data should
be written into FIFO first and then read from FIFO. There are two approaches to accessing the FIFO; one is to
directly access the FIFO using a CPU, the other is to access the FIFO using a DMA controller.
Espressif Systems 317 ESP32 TRM (Version 5.2)
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