Espressif ESP32 Technical Reference Manual page 146

7 SPI Controller (SPI)
31
0 0 0 0 0 0 0
SPI_SLV_WR_STATUS_REG In the slave mode this register is the status register for the master to
write the slave. In the master mode, if the address length is bigger than 32 bits,
stores the higher 32 bits of address value, and this register stores the rest lower part of address
value. (R/W)
31 30 29 28
0 0 0 0 0 0 0
SPI_CS_KEEP_ACTIVE This bit is only used in master mode where when it is set, the CS signal will
keep active. (R/W)
SPI_CK_IDLE_EDGE This bit is only used in master mode to configure the logicl level of SPI output
clock in idle state. (R/W)
1: the spi_clk line keeps high when idle;
0: the spi_clk line keeps low when idle.
SPI_MASTER_CK_SEL Reserved.
SPI_MASTER_CS_POL Reserved.
SPI_CK_DIS Reserved.
SPI_CS2_DIS This bit enables the SPI CS2 signal. 1: disables CS2; 0: enables CS2. (R/W)
SPI_CS1_DIS This bit enables the SPI CS1 signal. 1: disables CS1; 0: enables CS1. (R/W)
SPI_CS0_DIS This bit enables the SPI CS0 signal. 1: disables CS0; 0: enables CS0. (R/W)
Espressif Systems
Register 7.13. SPI_SLV_WR_STATUS_REG (0x30)
0 0 0 0 0 0 0 0
Register 7.14. SPI_PIN_REG (0x34)
0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0
14 13 11 10 9
0 0 0 0 0 0 0 0
146
0 0 0 0 0 0 0 0
SPI_ADDR_REG
8 6 5 4 3 2 1
0 0 0 0 0 0 0 0 1 1
ESP32 TRM (Version 5.2)
0
0
Reset
0
0
Reset