12 I2S Controller (I2S)
31
0
0
0
0
0
0
0
I2S_TX_STOP_EN Set this bit and the transmitter will stop transmitting BCK signal and WS signal
when tx FIFO is empty. (R/W)
I2S_RX_PCM_BYPASS Set this bit to bypass the Compress/Decompress module for the received
data. (R/W)
I2S_RX_PCM_CONF Compress/Decompress module configuration bit. (R/W)
0: Decompress received data;
1: Compress received data.
I2S_TX_PCM_BYPASS Set this bit to bypass the Compress/Decompress module for the transmitted
data. (R/W)
I2S_TX_PCM_CONF Compress/Decompress module configuration bit. (R/W)
0: Decompress transmitted data;
1: Compress transmitted data.
31
0
0
0
0
0
0
0
I2S_FIFO_FORCE_PU Force FIFO power-up. (R/W)
I2S_FIFO_FORCE_PD Force FIFO power-down. (R/W)
Espressif Systems
Register 12.28. I2S_CONF1_REG (0x00a0)
0
0
0
0
0
0
0
0
Register 12.29. I2S_PD_CONF_REG (0x00a4)
0
0
0
0
0
0
0
0
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9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
342
8
7
6
4
3
2
0
1
0x0
1
0x1
4
3
2
1
0
0
0
0
0
1
0
1
ESP32 TRM (Version 5.2)
0
Reset
0
0
Reset
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