Espressif ESP32 Technical Reference Manual page 327

12 I2S Controller (I2S)
• I2S_TX_REMPTY_INT: Triggered when the transmit FIFO is empty.
• I2S_TX_WFULL_INT: Triggered when the transmit FIFO is full.
• I2S_RX_REMPTY_INT: Triggered when the receive FIFO is empty.
• I2S_RX_WFULL_INT: Triggered when the receive FIFO is full.
• I2S_TX_PUT_DATA_INT: Triggered when the transmit FIFO is almost empty.
• I2S_RX_TAKE_DATA_INT: Triggered when the receive FIFO is almost full.
12.6.2 DMA Interrupts
• I2S_OUT_TOTAL_EOF_INT: Triggered when all transmitting linked lists are used up.
• I2S_IN_DSCR_EMPTY_INT: Triggered when there are no valid receiving linked lists left.
• I2S_OUT_DSCR_ERR_INT: Triggered when invalid txlink descriptors are encountered.
• I2S_IN_DSCR_ERR_INT: Triggered when invalid rxlink descriptors are encountered.
• I2S_OUT_EOF_INT: Triggered when txlink has finished sending a packet.
• I2S_OUT_DONE_INT: Triggered when all transmitted and buffered data have been read.
• I2S_IN_SUC_EOF_INT: Triggered when all data have been received.
• I2S_IN_DONE_INT: Triggered when the current rxlink descriptor is handled.
12.7 Register Summary
Name
I2S FIFO registers
I2S_FIFO_WR_REG
I2S_FIFO_RD_REG
Configuration registers
I2S_CONF_REG
I2S_CONF1_REG
I2S_CONF2_REG
I2S_TIMING_REG
I2S_FIFO_CONF_REG
I2S_CONF_SINGLE_DATA_REG
I2S_CONF_CHAN_REG
I2S_LC_HUNG_CONF_REG
I2S_CLKM_CONF_REG
I2S_SAMPLE_RATE_CONF_REG
I2S_PD_CONF_REG
I2S_STATE_REG
DMA registers
Espressif Systems
Description
Writes the data sent by I2S into
FIFO
Stores the data that I2S receives
from FIFO
Configuration and start/stop bits
PCM configuration register
ADC/LCD/camera configuration
register
Signal delay and timing parame-
ters
FIFO configuration
Static channel output value
Channel configuration
Timeout detection configuration
Bitclock configuration
Sample rate configuration
Power-down register
I2S status register
327
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I2S0 I2S1
0x3FF4F000 0x3FF6D000 WO
0x3FF4F004 0x3FF6D004 RO
0x3FF4F008 0x3FF6D008 R/W
0x3FF4F0A0 0x3FF6D0A0 R/W
0x3FF4F0A8 0x3FF6D0A8 R/W
0x3FF4F01C 0x3FF6D01C R/W
0x3FF4F020 0x3FF6D020 R/W
0x3FF4F028 0x3FF6D028 R/W
0x3FF4F02C 0x3FF6D02C R/W
0x3FF4F074 0x3FF6D074 R/W
0x3FF4F0AC 0x3FF6D0AC R/W
0x3FF4F0B0 0x3FF6D0B0 R/W
0x3FF4F0A4 0x3FF6D0A4 R/W
0x3FF4F0BC 0x3FF6D0BC RO
ESP32 TRM (Version 5.2)
Acc