Espressif ESP32 Technical Reference Manual page 320

12 I2S Controller (I2S)
For example, as is shown in Figure 12-7, if the width of serial data is 16 bits, when I2S_RX_RIGHT_FIRST equals
1, Data0 will be discarded and I2S will start receiving data from Data1. If I2S_RX_MSB_RIGHT equals 1, data
of the first stage would be {0xF EDC0000, 0x32100000}. If I2S_RX_MSB_RIGHT equals 0, data of the first
stage would be {0x32100000, 0xF EDC0000}. When I2S_RX_RIGHT_FIRST equals 0, I2S will start receiving
data from Data0. If I2S_RX_MSB_RIGHT equals 1, data of the first stage would be {0xF EDC0000, 0x76540000}.
If I2S_RX_MSB_RIGHT equals 0, data of the first stage would be {0x76540000, 0xF EDC0000}.
As is shown in Table 12-4
into FIFO. There are four modes of writing received data into FIFO. Each mode corresponds to a value of
I2S_RX_FIFO_MOD[2:0] bit.
Table 12-4. Modes of Writing Received Data into FIFO and the Corresponding Register Configuration
I2S_RX_FIFO_MOD[2:0]
0
1
2
3
At the third stage, CPU or DMA will read data from FIFO and write them into the internal memory directly. The
register configuration that each mode corresponds to is shown in Table 12-5.
Espressif Systems
Figure 12-7. The First Stage of Receiving Data
and Figure 12-8, at the second stage, the received data of the Rx unit is written
Figure 12-8. Modes of Writing Received Data into FIFO
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Data format
16-bit dual channel data
16-bit single channel data
32-bit dual channel data
32-bit single channel data
320 ESP32 TRM (Version 5.2)