Espressif ESP32 Technical Reference Manual page 133

7 SPI Controller (SPI)
To conclude, if signals do not pass through GPIO matrix, the SPI slave clock frequency is up to f
pass through GPIO matrix, the SPI slave clock frequency is up to f
output hold time for SPI slave in mode0 and mode2.
7.5 Parallel QSPI
ESP32 SPI controllers support SPI bus memory devices (such as flash and SRAM). The hardware connection
between the SPI pins and the memories is shown by Figure 7-5.
SPI1, SPI2 and SPI3 controllers can also be configured as QSPI master to connect to external memory. The
maximum output clock frequency of the SPI memory interface is f
of the GP-SPI master.
7.5.1 Communication Format of Parallel QSPI
To support communication with special slave devices, ESP32 QSPI implements a specifically designed com-
munication protocol. The communication format of ESP32 QSPI master is the same as that of GP-SPI four-line
half-duplex communication, except that in address phase and data phase, software can configure registers to
enable two-line or four-line transmission. Figure
mission in address phase and data phase.
Espressif Systems
Figure 7-4. GP-SPI
Figure 7-5. Parallel QSPI
7-6 shows a QSPI communication mode with four-line trans-
133
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/12. Note that (t
/2–t
apb spi
, with the same clock configuration as that
apb
ESP32 TRM (Version 5.2)
/8; if signals
apb
) represents data
pre