20 eFuse Controller
31
0
0
0
0
0
0
0
0
0
EFUSE_RD_CHIP_VER_PKG These are the first three identification bits of chip packaging version
among the four identification bits. (RO)
EFUSE_RD_SPI_PAD_CONFIG_HD This field returns the value of SPI_pad_config_hd. (RO)
EFUSE_RD_CHIP_VER_DIS_CACHE Disables cache. (RO)
EFUSE_RD_CHIP_VER_PKG This is the fourth identification bit of chip packaging version among the
four identification bits. (RO)
EFUSE_RD_CHIP_VER_DIS_BT Disables Bluetooth. (RO)
EFUSE_RD_CHIP_VER_DIS_APP_CPU Disables APP CPU. (RO)
31
0
0
0
0
0
0
0
EFUSE_RD_SDIO_FORCE This field returns the value of sdio_force. (RO)
EFUSE_RD_SDIO_TIEH This field returns the value of SDIO_TIEH. (RO)
EFUSE_RD_XPD_SDIO This field returns the value of XPD_SDIO_REG. (RO)
ESFUSE_RD_CK8M_FREQ RC_FAST_CLK frequency. (RO)
Espressif Systems
Register 20.4. EFUSE_BLK0_RDATA3_REG (0x00c)
0
0
0
0
0
0
0
0
0
Register 20.5. EFUSE_BLK0_RDATA4_REG (0x010)
17
16
0
0
0
0
0
0
0
0
0
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12
11
9
8
0
0
0
0
0
0
0
0
0
15
14
13
8
0
0
0
0
0
0
0
0
535
4
3
2
1
0
0
0
0
0
0
0
0
0
Reset
7
0
0
0
0
0
0
0
0
0
Reset
ESP32 TRM (Version 5.2)
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