Espressif ESP32 Technical Reference Manual page 634

28 Process ID Controller (PID)
31
PIDCTRL_INTERRUPT_ADDR_5_REG Level 5 interrupt vector entry address. (R/W)
31
PIDCTRL_INTERRUPT_ADDR_6_REG Level 6 interrupt vector entry address. (R/W)
31
PIDCTRL_INTERRUPT_ADDR_7_REG NMI interrupt vector entry address. (R/W)
31
0 0 0 0 0 0 0
PIDCTRL_PID_DELAY Delay until newly assigned PID is valid. (R/W)
31
0 0 0 0 0 0 0
PIDCTRL_NMI_DELAY Delay for disabling CPU NMI interrupt mask signal. (R/W)
Espressif Systems
Register 28.6. PIDCTRL_INTERRUPT_ADDR_5_REG (0x014)
0x040000240
Register 28.7. PIDCTRL_INTERRUPT_ADDR_6_REG (0x018)
0x040000280
Register 28.8. PIDCTRL_INTERRUPT_ADDR_7_REG (0x01C)
0x0400002C0
Register 28.9. PIDCTRL_PID_DELAY_REG (0x020)
0 0 0 0 0 0 0 0
Register 28.10. PIDCTRL_NMI_DELAY_REG (0x024)
0 0 0 0 0 0 0 0
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12 11
0 0 0 0 0
12 11
0 0 0 0 0
634
0
Reset
0
Reset
0
Reset
0
20 Reset
0
16 Reset
ESP32 TRM (Version 5.2)