Espressif ESP32 Technical Reference Manual page 305

11 I2C Controller (I2C)
31
0 0
I2C_NONFIFO_TX_THRES When I2C sends more than nonfifo_tx_thres bytes of data, it will generate
a tx_send_empty_int_raw interrupt and update the current offset address of the sent data. (R/W)
I2C_NONFIFO_RX_THRES When I2C receives more than nonfifo_rx_thres bytes of data, it will gen-
erate a rx_send_full_int_raw interrupt and update the current offset address of the received
data. (R/W)
I2C_FIFO_ADDR_CFG_EN When this bit is set to 1, the byte received after the I2C address byte
represents the offset address in the I2C Slave RAM. (R/W)
I2C_NONFIFO_EN Set this bit to enable APB nonfifo access. (R/W)
Espressif Systems
Register 11.7. I2C_FIFO_CONF_REG (0x0018)
26 25
0 0 0 0 0x15
Submit Documentation Feedback
20 19 14 13
0x15 0
305
12 11 10
0 0 0
Reset
ESP32 TRM (Version 5.2)