Espressif ESP32 Technical Reference Manual page 135

7 SPI Controller (SPI)
• SPI_OUTLINK_DSCR_ERROR_INT: Triggered when the linked list to be sent is invalid.
• SPI_INLINK_DSCR_EMPTY_INT: Triggered when no valid linked list is available.
7.7 Register Summary
Name
Control and configuration registers
SPI_CTRL_REG
SPI_CTRL2_REG
SPI_CLOCK_REG
SPI_PIN_REG
Slave mode configuration registers
SPI_SLAVE_REG
SPI_SLAVE1_REG
SPI_SLAVE2_REG
SPI_SLV_WR_STATUS_REG
SPI_SLV_WRBUF_DLEN_REG
SPI_SLV_RDBUF_DLEN_REG
SPI_SLV_RD_BIT_REG
User-defined command mode registers
SPI_CMD_REG
SPI_ADDR_REG
SPI_USER_REG
SPI_USER1_REG
SPI_USER2_REG
SPI_MOSI_DLEN_REG
SPI_W0_REG
SPI_W1_REG
Espressif Systems
Description
Bit order and
QIO/DIO/QOUT/DOUT
mode settings
Timing configuration
Clock configuration
Polarity and CS con-
figuration
Slave mode config-
uration and interrupt
status
Slave data bit
lengths
Dummy cycle length
configuration
Slave status/Part
of lower master
address
Write-buffer opera-
tion length
Read-buffer opera-
tion length
Read data operation
length
Start user-defined
command
Address data
User defined com-
mand configuration
Address and dummy
cycle configuration
Command length
and value configura-
tion
MOSI length
SPI data register 0
SPI data register 1
135
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SPI0 SPI1 SPI2
3FF43008 3FF42008 3FF64008 3FF65008 R/W
3FF43014 3FF42014 3FF64014 3FF65014 R/W
3FF43018 3FF42018 3FF64018 3FF65018 R/W
3FF43034 3FF42034 3FF64034 3FF65034 R/W
3FF43038 3FF42038 3FF64038 3FF65038 R/W
3FF4303C 3FF4203C 3FF6403C 3FF6503C R/W
3FF43040 3FF42040 3FF64040 3FF65040 R/W
3FF43030 3FF42030 3FF64030 3FF65030 R/W
3FF43048 3FF42048 3FF64048 3FF65048 R/W
3FF4304C 3FF4204C 3FF6404C 3FF6504C R/W
3FF43064 3FF42064 3FF64064 3FF65064 R/W
3FF43000 3FF42000 3FF64000 3FF65000 R/W
3FF43004 3FF42004 3FF64004 3FF65004 R/W
3FF4301C 3FF4201C 3FF6401C 3FF6501C R/W
3FF43020 3FF42020 3FF64020 3FF65020 R/W
3FF43024 3FF42024 3FF64024 3FF65024 R/W
3FF43028 3FF42028 3FF64028 3FF65028 R/W
3FF43080 3FF42080 3FF64080 3FF65080 R/W
3FF43084 3FF42084 3FF64084 3FF65084 R/W
ESP32 TRM (Version 5.2)
SPI3 Acc