Espressif ESP32 Technical Reference Manual page 542

20 eFuse Controller
31
0 0 0 0 0 0 0
EFUSE_OP_CODE eFuse operation code register. (R/W)
31
0 0 0 0 0 0 0
EFUSE_PGM_CMD Set this to 1 to start a program operation. Reverts to 0 when the program oper-
ation is done. (R/W)
EFUSE_READ_CMD Set this to 1 to start a read operation. Reverts to 0 when the read operation is
done. (R/W)
31
0 0 0 0 0 0 0
EFUSE_PGM_DONE_INT_RAW The raw interrupt status bit for the
rupt. (RO)
EFUSE_READ_DONE_INT_RAW The raw interrupt status bit for the
rupt. (RO)
Espressif Systems
Register 20.22. EFUSE_CONF_REG (0x0fc)
0 0 0 0 0 0 0 0
Register 20.23. EFUSE_CMD_REG (0x104)
0 0 0 0 0 0 0 0
Register 20.24. EFUSE_INT_RAW_REG (0x108)
0 0 0 0 0 0 0 0
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16 15
0 0x00000
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
EFUSE_PGM_DONE_INT
EFUSE_READ_DONE_INT
542
2 1
0 0 0 0 0 0 0 0
2 1
0 0 0 0 0 0 0 0
inter-
inter-
ESP32 TRM (Version 5.2)
0
Reset
0
0 Reset
0
0
Reset